NCP1207
PWM Current−Mode
Controller for Free RunningQuasi−Resonant Operation
The NCP1207 combines a true current mode modulator and ademagnetization detector to ensure full borderline/critical ConductionMode in any load/line conditions and minimum drain voltageswitching (Quasi−Resonant operation). Due to its inherent skip cyclecapability, the controller enters burst mode as soon as the powerdemand falls below a predetermined level. As this happens at low peakcurrent, no audible noise can be heard. An internal 8.0 ms timerprevents the free−run frequency to exceed 100 kHz (therefore belowthe 150 kHz CISPR−22 EMI starting limit), while the skip adjustmentcapability lets the user select the frequency at which the burst foldbacktakes place.
The Dynamic Self−Supply (DSS) drastically simplifies thetransformer design in avoiding the use of an auxiliary winding tosupply the NCP1207. This feature is particularly useful in applicationswhere the output voltage varies during operation (e.g. batterychargers). Due to its high−voltage technology, the IC is directlyconnected to the high−voltage DC rail. As a result, the short−circuittrip point is not dependent upon any VCC auxiliary level.
The transformer core reset detection is done through an auxiliarywinding which, brought via a dedicated pin, also enables fastOver−Voltage Protection (OVP). Once an OVP has been detected, theIC permanently latches−off.
Finally, the continuous feedback signal monitoring implementedwith an over−current fault protection circuitry (OCP) makes the finaldesign rugged and reliable.
Features
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MARKINGDIAGRAMS
8
SO−8
D1, D2 SUFFIXCASE 751
18
PDIP−8N SUFFIXCASE 626
811207/PAWL, LYY, YWW, W
1
= Device Code
= Assembly Location= Wafer Lot= Year
= Work Week
1207PAWLYYWW1207ALYW1
8PIN CONNECTIONS
DmgFBCSGnd
1234
(Top View)
8765
HVNCVCCDrv
••••••••••••••••••
Free−Running Borderline/Critical Mode Quasi−Resonant OperationCurrent−Mode with Adjustable Skip−Cycle CapabilityNo Auxiliary Winding VCC OperationAuto−Recovery Over Current ProtectionLatching Over Voltage Protection
External Latch Triggering, e.g. Via Over−Temperature Signal500 mA Peak Current Source/Sink CapabilityInternal 1.0 ms Soft−Start
Internal 8.0 ms Minimum TOFFAdjustable Skip Level
Internal Temperature ShutdownDirect Optocoupler Connection
SPICE Models Available for TRANsient AnalysisPb−Free Package is Available
AC/DC Adapters for Notebooks, etc.Offline Battery Chargers
Consumer Electronics (DVD Players, Set−Top Boxes, TVs, etc.)Auxiliary Power Supplies (USB, Appliances, TVs, etc.)
ORDERING INFORMATION
DeviceNCP1207DR2NCP1207DR2GNCP1207P
PackageSOIC−8SOIC−8(Pb−Free)PDIP−8
Shipping†2500/Tape & Reel2500/Tape & Reel50 Units/Tube
Typical Applications
†For information on tape and reel specifications,including part orientation and tape sizes, pleaserefer to our Tape and Reel Packaging SpecificationsBrochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 20041
February, 2004 − Rev. 5
Publication Order Number:
NCP1207/D
NCP1207
Vout++OVP andDemagNCP12071234Universal Network8765*Gnd+*Please refer to the application information sectionFigure 1. Typical Application
PIN FUNCTION DESCRIPTIONPin No.12Pin NameDemagFBFunctionCore reset detection and OVPSets the peak current setpointDescriptionThe auxiliary FLYBACK signal ensures discontinuous operation andoffers a fixed overvoltage detection level of 7.2 V.By connecting an Optocoupler to this pin, the peak current setpoint isadjusted accordingly to the output power demand. By bringing this pinbelow the internal skip level, device shuts off.This pin senses the primary current and routes it to the internalcomparator via an L.E.B. By inserting a resistor in series with the pin, youcontrol the level at which the skip operation takes place.−The driver’s output to an external MOSFET.This pin is connected to an external bulk capacitor of typically 10 mF.This unconnected pin ensures adequate creepage distance.Connected to the high−voltage rail, this pin injects a constant current intothe VCC bulk capacitor.3CSCurrent sense input and skipcycle level selectionThe IC groundDriving pulsesSupplies the IC−High−voltage pin45678GndDrvVCCNCHVhttp://onsemi.com
2
NCP1207
4.5 msDelayHV
7.0mA+−+VCC
12 V, 10 V,5.3 V (fault)−+PONDemagOVP+5.0 V/1.448.0 msBlankingSS*R*RQQVCC−++50 mVDriver: src = 20sink = 10Drv
4.2 VFaultMngt.RintResdDemag
10 VTo InternalSupplyGND
+−Overload?TimeoutResetSoft−Start = 1 ms1.0 V/3FB
200 mAwhen Drvis OFF380 nsL.E.B.CS
5.0 msTimeout*S and R are level triggered whereas S is edgetriggered. R has priority over the other inputs.DemagFigure 2. Internal Circuit Architecture
MAXIMUM RATINGSRatingPower Supply VoltageMaximum Voltage on all other pins except Pin 8 (HV), Pin 6 (VCC) Pin 5 (Drv) andPin 1 (Demag)Maximum Current into all pins except VCC (6), HV (8) and Demag (1) when 10 VESD diodes are activatedMaximum Current in Pin 1Thermal Resistance, Junction−to−CaseThermal Resistance, Junction−to−Air, SOIC versionThermal Resistance, Junction−to−Air, DIP8 versionMaximum Junction TemperatureTemperature ShutdownHysteresis in ShutdownStorage Temperature RangeESD Capability, HBM Model (All pins except HV)ESD Capability, Machine ModelMaximum Voltage on Pin 8 (HV), Pin 6 (VCC) decoupled to ground with 10 mFMinimum Voltage on Pin 8 (HV), Pin 6 (VCC) decoupled to ground with 10 mFSymbolVCC, Drv−−IdemRqJCRqJARqJATJMAX−−−−−VHVMAXVHVMINValue16−0.3 to 105.0+3.0/−2.05717810015015530−60 to +1502.020050040UnitsVVmAmA°C/W°C/W°C/W°C°C°C°CkVVVVhttp://onsemi.com
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NCP1207
ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = 0°C to +125°C, Max TJ = 150°C,
VCC = 11 V unless otherwise noted)
RatingDYNAMIC SELF−SUPPLY
Vcc Increasing Level at which the Current Source Turns−offVcc Decreasing Level at which the Current Source Turns−onVcc Decreasing Level at which the Latch−off Phase EndsInternal IC Consumption, No Output Load on Pin 5, FSW = 60 kHzInternal IC Consumption, 1.0 nF Output Load on Pin 5, FSW = 60 kHzInternal IC Consumption in Latch−off PhaseINTERNAL START−UP CURRENT SOURCE (TJ u 0°C)High−voltage Current Source, VCC = 10 VHigh−voltage Current Source, VCC = 0DRIVE OUTPUT
Output Voltage Rise−time @ CL = 1.0 nF, 10−90% of OutputSignalOutput Voltage Fall−time @ CL = 1.0 nF, 10−90% of OutputSignalSource ResistanceSink ResistanceCURRENT COMPARATOR (Pin 5 Unloaded)Input Bias Current @ 1.0 V Input Level on Pin 3Maximum Internal Current SetpointPropagation Delay from Current Detection to Gate OFF StateLeading Edge Blanking DurationInternal Current Offset Injected on the CS Pin during OFF TimeOVERVOLTAGE SECTION (VCC = 11 V)Sampling Delay after ON TimeOVP Internal Reference LevelFEEDBACK SECTION (VCC = 11 V, Pin 5 Loaded by 1.0 kW)Internal Pull−up ResistorPin 3 to Current Setpoint Division RatioInternal Soft−startDEMAGNETIZATION DETECTION BLOCKInput Threshold Voltage (Vpin 1 Decreasing)Hysteresis (Vpin 1 Decreasing)Input Clamp VoltageHigh State (Ipin 1 = 3.0 mA)Low State (Ipin 1 = −2.0 mA)Demag Propagation DelayInternal Input Capacitance at Vpin 1 = 1.0 VMinimum TOFF (Internal Blanking Delay after TON)Timeout After Last Demag TransitionPin 1 Internal Impedance1.Max value at TJ = 0°C.111111111VthVHVCHVCLTdemCparTblankToutRint35−8.0−0.9−−−−−502010−0.7210108.05.02890−12−0.5−−−−−mVmVVVnspFmsmskW2−−RupIratioTss−−−203.31.0−−−kW−ms11TsampleVref−6.44.57.2−8.0msV33333IIBILimitTDELTLEBIskip−0.92−−−0.021.0100380200−1.12160−−mAVnsnsmA5555TrTfROHROL−−125.040202010−−3619nsnsWW88IC1IC24.3−7.08.09.6−mAmA666666VCCOFFVCCONVCClatchICC1ICC2ICC310.89.1−−−−12105.31.01.633012.910.6−1.3(Note 1)2.0(Note 1)−VVVmAmAmAPinSymbolMinTypMaxUnithttp://onsemi.com
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NCP1207
13.212.812.4VCCOFF (V)12.011.611.210.810.4
−25
0
25
50
75
100
125
VCCON (V)11.210.810.4109.69.28.8−25
0255075100125
TEMPERATURE (°C)TEMPERATURE (°C)
Figure 3. VCCOFF Threshold versus
Temperature
1.61.41.2ICC1 (mA)1.00.80.60.4−25
ICC2 (mA)2.32.11.91.71.51.31.1−25
Figure 4. VCCON Threshold versus
Temperature
02550751001250255075100125
TEMPERATURE (°C)TEMPERATURE (°C)
Figure 5. Current Consumption (No Load)
versus Temperature
1210
1.201.151.10
IC1 (mA)Ilimit (V)8.0
1.051.00
4.02.0−25
0.950.90
−25
Figure 6. Current Consumption (Loaded by
1 nF) versus Temperature
6.0
02550751001250255075100125
TEMPERATURE (°C)TEMPERATURE (°C)
Figure 7. HV Current Source at VCC = 10 V
versus TemperatureFigure 8. Maximum Current Setpoint versus
Temperature
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NCP1207
403530ROH (W)ROL (W)0
25
50
75
100
125
2520151050−25
2018161412108.06.04.02.00−25
0255075100125
TEMPERATURE (°C)TEMPERATURE (°C)
Figure 9. Drive Source Resistance versus
Temperature
120100
7.5
80VTH (mV)6040
6.5
200−25
6.0−25Vref (V)7.08.0
Figure 10. Drive Sink Resistance versus
Temperature
02550751001250255075100125
TEMPERATURE (°C)TEMPERATURE (°C)
Figure 11. Demagnetization Detection
Threshold versus Temperature
109.59.0Toff (ms)8.58.07.57.06.5−25
0
25
50
75
100
125
Tout (ms)7.06.66.25.85.45.04.64.2
Figure 12. OVP Threshold versus Temperature
3.8−25
0255075100125
TEMPERATURE (°C)TEMPERATURE (°C)
Figure 13. Minimum Toff versus Temperature
Figure 14. Demagnetization Detection Timeout
versus Temperature
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NCP1207
1.51.41.3Tss (ms)1.21.11.00.90.8−25
0
25
50
75
100
125
Rint (kW)6050403020100−25
0255075100125
TEMPERATURE (°C)TEMPERATURE (°C)
Figure 15. Internal Soft−start versus
TemperatureFigure 16. DMG Pin Internal Resistance versus
Temperature
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NCP1207
Application Information
Introduction
The NCP1207 implements a standard current modearchitecture where the switch−off time is dictated by thepeak current setpoint whereas the core reset detectiontriggers the turn−on event. This component represents theideal candidate where low part−count is the key parameter,particularly in low−cost AC/DC adapters, consumerelectronics, auxiliary supplies, etc. Thanks to itshigh−performance High−Voltage technology, the NCP1207incorporates all the necessary components / features neededto build a rugged and reliable Switch−Mode Power Supply(SMPS):
occurs at low peak current. This point guarantees anoise−free operation with cheap transformer. Thisoption also offers the ability to fix the maximumswitching frequency when entering light loadconditions.
Over Current Protection (OCP): by continuouslymonitoring the FB line activity, NCP1207 enters burstmode as soon as the power supply undergoes an
overload. The device enters a safe low power operationwhich prevents from any lethal thermal runaway. Assoon as the default disappears, the power supply
resumes operation. Unlike other controllers, overloaddetection is performed independently of any auxiliarywinding level. In presence of a bad coupling betweenboth power and auxiliary windings, the short circuitdetection can be severely affected. The DSS naturallyshields you against these troubles.
•
•Transformer core reset detection: borderline / critical
operation is ensured whatever the operating conditionsare. As a result, there are virtually no primary switchturn−on losses and no secondary diode recovery losses.The converter also stays a first−order system andaccordingly eases the feedback loop design.Quasi−resonant operation: by delaying the turn−onevent, it is possible to re−start the MOSFET in theminimum of the drain−source wave, ensuring reducedEMI / video noise perturbations. In nominal powerconditions, the NCP1207 operates in BorderlineConduction Mode (BCM) also called CriticalConduction Mode.
Dynamic Self−Supply (DSS): due to its Very HighVoltage Integrated Circuit (VHVIC) technology,
ONSemiconductor’s NCP1207 allows for a direct pinconnection to the high−voltage DC rail. A dynamiccurrent source charges up a capacitor and thus providesa fully independent VCC level to the NCP1207. As aresult, there is no need for an auxiliary winding whosemanagement is always a problem in variable outputvoltage designs (e.g. battery chargers).
Overvoltage Protection (OVP): by sampling the plateauvoltage on the demagnetization winding, the NCP1207goes into latched fault condition whenever an
over−voltage condition is detected. The controller staysfully latched in this position until the VCC is cycleddown 4.0 V, e.g. when the user un−plugs the powersupply from the mains outlet and re−plugs it.
External latch trip point: by externally forcing a levelon the OVP greater than the internal setpoint, it ispossible to latch−off the IC, e.g. with a signal comingfrom a temperature sensor.
Adjustable skip cycle level: by offering the ability totailor the level at which the skip cycle takes place, thedesigner can make sure that the skip operation only
•
•
Dynamic Self−Supply
The DSS principle is based on the charge/discharge of theVCC bulk capacitor from a low level up to a higher level. Wecan easily describe the current source operation with somesimple logical equations:
POWER−ON: IF VCC < VCCOFF THEN Current Sourceis ON, no output pulses
IF VCC decreasing > VCCON THEN Current Source isOFF, output is pulsing
IF VCC increasing < VCCOFF THEN Current Source isON, output is pulsing
Typical values are: VCCOFF = 12 V, VCCON = 10 VTo better understand the operational principle, Figure 17’ssketch offers the necessary light.
VRIPPLE = 2 VVCC•
VCCOFF = 12 VVCCON = 10 V•
CURRENTSOURCEONOFFOutput Pulses•
Figure 17. The Charge/Discharge Cycle Over a 10 mF
VCC Capacitor
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NCP1207
The DSS behavior actually depends on the internal ICconsumption and the MOSFET’s gate charge Qg. If weselect a MOSFET like the MTP2N60E, Qg equals 22nC(max). With a maximum switching frequency selected at75kHz, the average power necessary to drive the MOSFET(excluding the driver efficiency and neglecting variousvoltage drops) is:
Fsw ⋅ Qg ⋅ VCC with:
Fsw = maximum switching frequencyQg = MOSFET’s gate charge
VCC = VGS level applied to the gate
To obtain the output current, simply divide this result byVCC: Idriver = FSW ⋅ Qg = 1.6 mA. The total standby powerconsumption at no−load will therefore heavily rely on theinternal IC consumption plus the above driving current(altered by the driver’s efficiency). Suppose that the IC issupplied from a 350 VDC line. The current flowing throughpin 8 is a direct image of the NCP1207 consumption(neglecting the switching losses of the HV current source).If ICC2 equals 2.3 mA @ TJ = 60°C, then the powerdissipated (lost) by the IC is simply: 350 V x 2.3 mA =805mW. For design and reliability reasons, it would beinterested to reduce this source of wasted power thatincrease the die temperature. This can be achieved by usingdifferent methods:
1.Use a MOSFET with lower gate charge Qg.
2.Connect pin 8 through a diode (1N4007 typically) toone of the mains input. The average value on pin 8
@2. Our power contributionbecomes mainsPEAKpexample drops to: 223 V x 2.3 mA = 512mW. If aresistor is installed between the mains and the diode,you further force the dissipation to migrate from thepackage to the resistor. The resistor value shouldaccount for low−line startups.
HV5When using Figure 18 option, it is important to checkthe absence of any negative ringing that could occuron pin 8. The resistor in series should help to dampany parasitic LC network that would ring whensuddenly applying the power to the IC. Also, sincethe power disappears during 10ms (half−waverectification), CVCC should be calculated to supplythe IC during these holes in the supply
3.Permanently force the VCC level above VCCH withan auxiliary winding. It will automaticallydisconnect the internal start−up source and the ICwill be fully self−supplied from this winding. Again,the total power drawn from the mains willsignificantly decrease. Make sure the auxiliaryvoltage never exceeds the 16 V limit.Skipping Cycle Mode
The NCP1207 automatically skips switching cycles whenthe output power demand drops below a given level. This isaccomplished by monitoring the FB pin. In normaloperation, pin 2 imposes a peak current accordingly to theload value. If the load demand decreases, the internal loopasks for less peak current. When this setpoint reaches adetermined level, the IC prevents the current fromdecreasing further down and starts to blank the outputpulses: the IC enters the so−called skip cycle mode, alsonamed controlled burst operation. The power transfer nowdepends upon the width of the pulse bunches (Figure 19) andfollows the following formula:
1@Lp@Ip2@Fsw@D
burst with:2V
Lp = primary inductance
Fsw = switching frequency within the burstIp = peak current at which skip cycle occursDburst = burst width / burst recurrence
MAX PEAKCURRENTNORMAL CURRENTMODE OPERATIONSKIP CYCLECURRENT LIMIT1N4007CURRENT SENSE SIGNAL (mV)300MAINS12Cbulk123487656
200100Figure 18. A simple diode naturally reduces the
average voltage on pin 8
0WIDTHRECURRENCEFigure 19. The skip cycle takes place at low peakcurrents which guaranties noise free operation
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NCP1207
DRIVERDRIVER = HIGH ? I = 0DRIVER = LOW ? I = 200 mA
−+3RskipRESET
2Rsense
+Figure 20. A patented method allows for skip levelselection via a series resistor inserted in series
with the current
The skip level selection is done through a simple resistorinserted between the current sense input and the sense element.Every time the NCP1207 output driver goes low, a 200mAsource forces a current to flow through the sense pin(Figure20): when the driver is high, the current source is offand the current sense information is normally processed. Assoon as the driver goes low, the current source delivers 200mAand develops a ground referenced voltage across Rskip. If thisvoltage is below the feedback voltage, the current sensecomparator stays in the high state and the internal latch can betriggered by the next clock cycle. Now, if because of a low loadmode the feedback voltage is below Rskip level, then the
current sense comparator permanently resets the latch and thenext clock cycle (given by the demagnetization detection) isignored: we are skipping cycles as shown by Figure 21. Assoon as the feedback voltage goes up again, there can be twosituations: the recurrent period is small and a newdemagnetization detection (next wave) signal triggers theNCP1207. To the opposite, in low output power conditions, nomore ringing waves are present on the drain and the togglingof the current sense comparator together with the internal 5 mstimeout initiates a new cycle start. In normal operatingconditions, e.g. when the drain oscillations are generous, thedemagnetization comparator can detect the 50 mV crossingand gives the “green light”, alone, to re−active the powerswitch. However, when skip cycle takes place (e.g. at lowoutput power demands), the re−start event slides along thedrain ringing waveforms (actually the valley locations) whichdecays more or less quickly, depending on theLprimary−Cparasitic network damping factor. The situation canthus quickly occur where the ringing becomes too weak to bedetected by the demagnetization comparator: it thenpermanently stays locked in a given position and can no longerdeliver the “green light” to the controller. To help in thissituation, the NCP1207 implements a 5 ms timeout generator:each time the 50 mV crossing occurs, the timeout is reset. So,as long as the ringing becomes too low, the timeout generatorstarts to count and after 5 ms, it delivers its “green light”. If theskip signal is already present then the controller re−starts;otherwise the logic waits for it to set the drive output high.Figure 21 depicts these two different situations:
DrainSignal
TimeoutSignal
Demag Re−startCurrent Sense and Timeout Re−startDrainSignal
TimeoutSignal
5 ms5 msFigure 21. When the primary natural ringing becomes too low, the internal timeout together with the sense
comparator initiates a new cycle when FB passes the skip level.
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NCP1207
Demagnetization Detection
The core reset detection is done by monitoring the voltageactivity on the auxiliary winding. This voltage features aFLYBACK polarity. The typical detection level is fixed at50mV as exemplified by Figure 22.
7.0DEMAG SIGNAL (V)POSSIBLERE−STARTS400DRAIN VOLTAGE (V)300
200
1000
5.0
3.0
1.0
0 VFigure 24. The NCP1207 Operates inBorderline / Critical Operation
50 mV−1.0
Figure 22. Core reset detection is done through a
dedicated auxiliary winding monitoring
TO INTERNALCOMPARATOR2Resd11Rdem54Overvoltage Protection
The overvoltage protection works by sampling the plateauvoltage 4.5 ms after the turn−off sequence. This delayguarantees a clean plateau, providing that the leakageinductance ringing has been fully damped. If this would notbe the case, the designer should install a small RC damperacross the transformer primary inductance connections.Figure 25 shows where the sampling occurs on the auxiliarywinding.8.0DEMAG SIGNAL (V)SAMPLING HERERintESD2ESD14Aux3Resd + Rint = 28 kFigure 23. Internal Pad Implementation
6.0An internal timer prevents any re−start within 8.0 msfurther to the driver going−low transition. This prevents theswitching frequency to exceed (1 / (TON + 8.0 ms)) but alsoavoid false leakage inductance tripping at turn−off. In somecases, the leakage inductance kick is so energetic, that aslight filtering is necessary.
The 1207 demagnetization detection pad features aspecific component arrangement as detailed by Figure 23. Inthis picture, the zener diodes network protect the IC againstany potential ESD discharge that could appear on the pins.The first ESD diode connected to the pad, exhibits a parasiticcapacitance. When this parasitic capacitance (10pFtypically) is combined with Rdem, a re−start delay is createdand the possibility to switch right in the drain−source waveexists. This guarantees QR operation with all the associatedbenefits (low EMI, no turn−on losses etc.). Rdem should becalculated to limit the maximum current flowing throughpin 1 to less than +3 mA/−2 mA. If during turn−on, theauxiliary winding delivers 30 V (at the highest line level),then the minimum Rdem value is defined by: (30 V + 0.7 V)/ 2mA = 14.6 kW. This value will be further increased tointroduce a re−start delay and also a slight filtering in caseof high leakage energy.
Figure 24 portrays a typical VDS shot at nominal outputpower.
4.02.04.5 ms0Figure 25. A voltage sample is taken 4.5 ms after
the turn−off sequence
When an OVP condition has been detected, the NCP1207enters a latch−off phase and stops all switching operations.The controller stays fully latched in this position and theDSS is still active, keeping the VCC between 5.3 V/12 V asin normal operations. This state lasts until the VCC is cycleddown 4 V, e.g. when the user unplugs the power supply fromthe mains outlet.
By default, the OVP comparator is biased to a 5Vreference level and pin1 is routed via a divide by 1.44network. As a result, when Vpin1 reaches 7.2V, the OVPcomparator is triggered. The threshold can thus be adjustedby either modifying the power winding to auxiliary windingturn ratios to match this 7.2V level, or insert a resistor frompin1 to ground to cope with your design requirement.
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NCP1207
Latching Off the NCP1207
In certain cases, it can be very convenient to externallyshut down permanently the NCP1207 via a dedicated signal,e.g. coming from a temperature sensor. The reset occurswhen the user unplugs the power supply from the mainsoutlet. To trigger the latch−off, a CTN (Figure 26) or asimple NPN transistor (Figure 27) can do the work.
CTNNCP120712348765AuxFigure 26. A simple CTN triggers the latch−off assoon as the temperature exceeds a given setpoint
NCP120712ON/OFF348765AuxPower Dissipation
The NCP1207 is directly supplied from the DC railthrough the internal DSS circuitry. The DSS being anauto−adaptive circuit (e.g. the ON/OFF duty−cycle adjustsitself depending on the current demand), the current flowingthrough the DSS is therefore the direct image of theNCP1207 current consumption. The total power dissipationcan be evaluated using: (VHVDC*11V)@ICC2. If weoperate the device on a 250 Vac rail, the maximum rectifiedvoltage can go up to 350 Vdc. As a result, the worse casedissipation occurs at the maximum switching frequency andthe highest line. The dissipation is actually given by theinternal consumption of the NCP1207 when driving theselected MOSFET. The best method to evaluate this totalconsumption is probably to run the final circuit from a50 Vdc source applied to pin 8 and measure the averagecurrent flowing into this pin. Suppose that we find 2.0 mA,meaning that the DSS duty−cycle will be 2.0/7.0 = 28.6%.From the 350 Vdc rail, the part will dissipate:350V@2.0mA+700mW (however this 2.0 mA numberwill drop at higher operating junction temperatures).A DIP8 package offers a junction−to−ambient thermalresistance RqJA of 100°C/W. The maximum powerdissipation can thus be computed knowing the maximumoperating ambient temperature (e.g. 70°C) together withthe maximum allowable junction temperature (125°C):
Pmax+
Tjmax*TAmax
t550mW. As we can see, we
RqJA
Figure 27. A simple transistor arrangement allowsto trigger the latch−off by an external signal
Shutting Off the NCP1207
Shutdown can easily be implemented through a simpleNPN bipolar transistor as depicted by Figure 28. When OFF,Q1 is transparent to the operation. When forward biased, thetransistor pulls the FB pin to ground (VCE(sat) ≈ 200 mV) andpermanently disables the IC. A small time constant on thetransistor base will avoid false triggering (Figure 28).
NCP1207110 kON/OFF32do not reach the worse consumption budget imposed by theoperating conditions. Several solutions exist to cure thistrouble:
•The first one consists in adding some copper area aroundthe NCP1207 DIP8 footprint. By adding a min pad areaof 80 mm2 of 35 mm copper (1 oz.), RqJA drops to about75°C/W. Maximum power then grows up to 730 mW.•A resistor Rdrop needs to be inserted with pin 8 toa) avoid negative spikes at turn−off (see below)
b) split the power budget between this resistor and thepackage. The resistor is calculated by leaving at least 50 Von pin 8 at minimum input voltage (suppose 100 Vdc in
V*50V
our case): Rdropvbulkmint7.1kW. The
power dissipated by the resistor is thus:
Pdrop+VdropRMS2ńRdrop
7.0mA
8765Q11234++
ǒIDSS@Rdrop@ǸDSSduty*cycleǓRdrop
2
ǒ7.0mA@7.1kW@Ǹ0.286Ǔ7.1kW
2
10 nF+99.5mW
Figure 28. A simple bipolar transistor totally
disables the IC
Please refer to the application note AND8069 availablefrom www.onsemi.com/pub/ncp1200.
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NCP1207
•If the power consumption budget is really too high for the
DSS alone, connect a diode between the auxiliarywinding and the VCC pin which will disable the DSSoperation (VCC u 10 V).
The SOIC package offers a 178°C/W thermal resistor.Again, adding some copper area around the PCB footprintwill help decrease this number: 12 mm 12 mm to dropRqJA down to 100°C/W with 35 mm copper thickness (1 oz.)or 6.5 mm 6.5 mm with 70 mm copper thickness (2 oz.).As one can see, we do not recommend using the SO−8package and the DSS if the part operates at high switchingfrequencies. In that case, an auxiliary winding is the bestsolution.
Overload Operation
In applications where the output current is purposely notcontrolled (e.g. wall adapters delivering raw DC level), it isinteresting to implement a true short−circuit protection. Ashort−circuit actually forces the output voltage to be at a lowlevel, preventing a bias current to circulate in theOptocoupler LED. As a result, the FB pin level is pulled upto 4.2 V, as internally imposed by the IC. The peak currentsetpoint goes to the maximum and the supply delivers arather high power with all the associated effects. Please notethat this can also happen in case of feedback loss, e.g. abroken Optocoupler. To account for this situation, NCP1207
VCCREGULATIONOCCURS HERELATCH−OFFPHASEhosts a dedicated overload detection circuitry. Onceactivated, this circuitry imposes to deliver pulses in a burstmanner with a low duty−cycle. The system recovers whenthe fault condition disappears.
During the start−up phase, the peak current is pushed tothe maximum until the output voltage reaches its target andthe feedback loop takes over. This period of time depends onnormal output load conditions and the maximum peakcurrent allowed by the system. The time−out used by this ICworks with the VCC decoupling capacitor: as soon as theVCC decreases from the VCCOFF level (typically 12 V) thedevice internally watches for an overload current situation.If this condition is still present when the VCCON level isreached, the controller stops the driving pulses, prevents theself−supply current source to restart and puts all the circuitryin standby, consuming as little as 330 mA typical (ICC3parameter). As a result, the VCC level slowly dischargestoward 0. When this level crosses 5.3 V typical, thecontroller enters a new startup phase by turning the currentsource on: VCC rises toward 12 V and again delivers outputpulses at the VCCOFF crossing point. If the fault conditionhas been removed before VCCON approaches, then the ICcontinues its normal operation. Otherwise, a new fault cycletakes place. Figure 29 shows the evolution of the signals inpresence of a fault.
12 V10 V5.3 V
TIME
DRVDRIVERPULSESTIME
INTERNALIf the fault is relaxed during the Vccnatural fall down sequence, the ICautomatically resumes.
If the fault still persists when Vccreached VCCON, then the controllercuts everything off until recovery.
FAULT FLAGFAULT ISRELAXEDSTARTUP PHASEFAULT OCCURS HERETIME
Figure 29.
Soft−Start
The NCP1207 features an internal 1 ms soft−start to softenthe constraints occurring in the power supply duringstart−up. It is activated during the power on sequence. Assoon as VCC reaches VCCOFF , the peak current is graduallyincreased from nearly zero up to the maximum clampinglevel (e.g. 1.0 V). The soft−start is also activated during theover current burst (OCP) sequence. Every restart attempt isfollowed by a soft−start activation. Generally speaking, thesoft−start will be activated when VCC ramps up either fromzero (fresh power−on sequence) or 5.3 V, the latch−offvoltage occurring during OCP.
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NCP1207
Calculating the Vcc Capacitor
As the above section describes, the fall down sequencedepends upon the VCC level: how long does it take for theVCC line to go from 12 V to 10 V? The required time dependson the start−up sequence of your system, i.e. when you firstapply the power to the IC. The corresponding transient faultduration due to the output capacitor charging must be lessthan the time needed to discharge from 12V to 10V,otherwise the supply will not properly start. The test consistsin either simulating or measuring in the lab how much timethe system takes to reach the regulation at full load. Let’ssuppose that this time corresponds to 6.0ms. Therefore aVCC fall time of 10ms could be well appropriated in orderto not trigger the overload detection circuitry. If thecorresponding IC consumption, including the MOSFETdrive, establishes at 1.8 mA (e.g. with an 11 nC MOSFET),we can calculate the required capacitor using the followingformula: Dt+DV@C, with DV = 2.0V. Then for a wantedDt of 10 ms, C equals 9.0 mF or 22 mF for a standard value.When an overload condition occurs, the IC blocks itsinternal circuitry and its consumption drops to 330mAtypical. This happens at VCC = 10V and it remains stuckuntil VCC reaches 5.3V: we are in latch−off phase. Again,using the calculated 22mF and 330mA current consumption,this latch−off phase lasts: 313ms.
HV Pin Recommended Protection
When the user unplugs a power supply built with a QRcontroller such as the NCP1207, two phenomena canappear:
1.A negative ringing can take place on pin8 due to aresonance between the primary inductance andthe bulk capacitor. As any CMOS device, theNCP1207 is sensitive to negative voltages thatcould appear on it’s pins and could create aninternal latch−up condition.
2.When the bulk capacitor discharges, the internallatch is reset by the voltage developed over thesense resistor and the ON time expands as lessvoltage is available. When the high−voltage railbecomes too low, the gate drives permanentlystays high since no reset occurs. This situation isnot desirable in many applications.
For the above reasons, we strongly recommend to add ahigh−voltage diode like a 1N4007 between the bulkcapacitor and the VCC pin. When the bulk level collapses, itnaturally shuts the controller down and eradicates the twoabove problems.
i
HVNCP1207+Cbulk12348765+D11N4007Figure 30.
Operation Shots
Below are some oscilloscope shots captured atVin = 120VDC with a transformer featuring a 800mHprimary inductance.
Figure 31.
This plot gathers waveforms captured at three differentoperating points:
1st upper plot: free run, valley switching operation,Pout = 26 W
2nd middle plot: min Toff clamps the switching frequencyand selects the second valley
3rd lowest plot: the skip slices the second valley patternand will further expand the burst as Pout goes low
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NCP1207
VGATE (5 V/div)VRsense (200 mV/div)VCC (5 V/div)200 mA X RSKIPVGATE (5 V/div)Current Sense Pin (200 mV/div)
Figure 32. Figure 33.
This picture explains how the 200 mA internal offsetcurrent creates the skip cycle level.The short−circuit protection forces the IC to enter burst inpresence of a secondary overload.
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NCP1207
PACKAGE DIMENSIONS
PDIP−8N SUFFIXCASE 626−05ISSUE L85−B−14NOTES:
1.DIMENSION L TO CENTER OF LEAD WHENFORMED PARALLEL.
2.PACKAGE CONTOUR OPTIONAL (ROUND ORSQUARE CORNERS).
3.DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.
DIMABCDFGHJKLMNMILLIMETERSMINMAX9.4010.166.106.603.944.450.380.511.021.782.54 BSC0.761.270.200.302.923.437.62 BSC−−−10 _0.761.01INCHESMINMAX0.3700.4000.2400.2600.1550.1750.0150.0200.0400.0700.100 BSC0.0300.0500.0080.0120.1150.1350.300 BSC−−−10 _0.0300.040FNOTE 2−A−LC−T−SEATINGPLANEJNDKMMTAMHG0.13 (0.005)BMhttp://onsemi.com
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NCP1207
PACKAGE DIMENSIONS
(SO−8)D1, D2 SUFFIXCASE 751−07ISSUE AA
−X−A85NOTES:
1.DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.
2.CONTROLLING DIMENSION: MILLIMETER.3.DIMENSION A AND B DO NOT INCLUDE MOLDPROTRUSION.
4.MAXIMUM MOLD PROTRUSION 0.15 (0.006) PERSIDE.
5.DIMENSION D DOES NOT INCLUDE DAMBARPROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL INEXCESS OF THE D DIMENSION AT MAXIMUMMATERIAL CONDITION.
6.751−01 THRU 751−06 ARE OBSOLETE. NEWSTANDAARD IS 751−07
MILLIMETERSMINMAX4.805.003.804.001.351.750.330.511.27 BSC0.100.250.190.250.401.270 _8 _0.250.505.806.20INCHESMINMAX0.1890.1970.1500.1570.0530.0690.0130.0200.050 BSC0.0040.0100.0070.0100.0160.0500 _8 _0.0100.0200.2280.244B1S40.25 (0.010)MYM−Y−GKC−Z−HD0.25 (0.010)
MSEATINGPLANENX 45_0.10 (0.004)MJZY
SX
SDIMABCDGHJKMNSSOLDERING FOOTPRINT*
1.520.0607.00.2754.00.1550.60.0241.2700.050SCALE 6:1
mmǓǒinches
SO−8
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering andMounting Techniques Reference Manual, SOLDERRM/D.
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NCP1207
The product described herein (NCP1207), may be covered by one or more of the following U.S. patents: 6,385,060; 6,385,061. There may be other patentspending.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further noticeto any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liabilityarising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. Alloperating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rightsnor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicationsintended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. ShouldBuyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or deathassociated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an EqualOpportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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