专利名称：Semiconductor device having a trench gate
structure and manufacturing method of thesame
发明人：Eiichi Taketani,Seigo Oosawa申请号：US13443059申请日：20120410公开号：US09136335B2公开日：20150915
专利附图：
摘要：In a manufacturing method of a semiconductor device, a trench is defined in asemiconductor substrate, and an adjuster layer having a first conductivity type impurity
concentration higher than a drift layer is formed at a portion of the semiconductorsubstrate adjacent to a bottom wall of the trench. A channel layer is formed byintroducing second conductivity type impurities to a portion of the semiconductorsubstrate adjacent to a sidewall of the trench and between the adjustment layer and amain surface of the semiconductor substrate while restricting the channel layer fromextending in a depth direction of the trench by the adjustment layer.
申请人：Eiichi Taketani,Seigo Oosawa
地址：Nukata-gun JP,Nukata-gun JP
国籍：JP,JP
代理机构：Posz Law Group, PLC
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