EDA英文练习部分答案0

1-2 Explanation of the terms listed below bilingual. ASIC PLD EDA CPLD FPGA HDL

solution：

ASIC：application-specific integrated circuit,专用集成电路 PLD: programmable logic devices，可编程逻辑器件 EDA: electronic design automation，电子设计自动化

CPLD：complex programmable logic devices，复杂可编程逻辑器件 FPGA: field-programmable gate array，现场可编程门阵列 HDL: hardware description language， 硬件描述语言 PART 2

2-2. Give a brief description of the top-down design flow.

solution：

System level & function level designFunction simulationsynthesisEDA toolsGate level netlistTiming simulation 2-3. Give a brief description of the Design flow when using PLD/FPGA.

solution：

Design Entry: Schematic HDL synthesisFunctional simulationFPGA/CPLD FitterTiming simulationFPGA/CPLD programOnline test

2-4. Give a brief description of the architecture of CPLD.

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solution：

2-5. Give a brief description of the architecture of FPGA. solution：

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2-6. Give a brief description of the differences between CPLD and FPGA. solution：

CPLD is based on gate array. It has and array and or array. After programmed, it can work all along. Every time it power on, it can work at once.

FPGA: is one kind of PLD, based on LUT technology. When it power off, the entire configuration is lost. And when it power on, reconfiguration is needed.

2-1. Describe two basic types of digital design methodologies in VHDL

solution：

There are two basic types of digital design methodologies: a top-down design

methodology and a bottom-up design methodology. In a top-down design methodology, we define the top-level block and identify the sub-blocks necessary to build the top-level block. We further subdivide the sub-blocks until we come to leaf cells, which are the cells that cannot further be divided. Figure 2-1 shows the top-down design process.

Figure 2-1. Top-down Design Methodology

In a

bottom-up

design methodology, we first identify the building blocks that are available to us. We build bigger cells, using these building blocks. These cells are then used for higher-level blocks until we build the top-level block in the design. Figure 2-2 shows the bottom-up design process.

Figure 2-2. Bottom-up Design Methodology

Typically, a combination of top-down and bottom-up flows is used. Design architects define the specifications of the top-level block. Logic designers decide how the design should be structured by breaking up the functionality into blocks and sub-blocks. At the same time, circuit designers are designing optimized circuits for leaf-level cells. They build higher-level cells by using these leaf cells. The flow meets at an intermediate point where the switch-level circuit designers have created a library of leaf cells by using switches, and the logic level designers have designed from top-down until all modules are defined in terms of leaf cells.

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PART 3

3-1．Fill in blank（填空题）

1. VHDL file type have 、 、 、 . 2. In graphic editor, the filename extension is ,which stands for graphic design file . 3. When using waveform editor, a file with extension stores the waveforms that will be used as simulation test vectors .

4. In text editor, the filename extension must be used for all files that contain VHDL code.

Solutions:

1．Graphic editor file, symbol editor file, text editor file, waveform editor file 2．gdf 3．scf 4．Vhdl

3-6. Write completely vhdl language description for half adder with assign statement (写出半加器完整的语言描述,用赋值语句)。 答案见实验指导书

3-7 Write completely vhdl language description for 8 bits adder. 8位全加器，答案见实验指导书

3-8 Write completely vhdl language description for 16 bits divider. 16位分频器，答案参见实验指导书 其余略

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