This version: Aug. 1998ML7000-01/02/03/ML7001-01/02/03inimaryGENERAL DESCRIPTION
The ML7000/ML7001 are single-channel CMOS CODEC LSI devices for voice signals rangingfrom 300 to 3400 Hz with filters for A/D and D/A conversion.
Designed especially for a single-power supply and low-power applications, the devices areoptimized for ISDN terminals, digital wireless systems, and digital PBXs.The devices use the same transmission clocks as those used in the MSM7507.
With the differential analog signal outputs which can drive 60 W load, the devices can directlydrive a handset receiver.
FEATURES
•Single power supply:+5 V (ML7000-xx)
+3 V (ML7001-xx)
•Low power consumptionOperating mode:25 mW Typ.VDD = 5.0 V (ML7000-xx)
20 mW Typ.VDD = 3.0 V (ML7001-xx)
Power-down mode:0.05 mW Typ.VDD = 5.0 V (ML7000-xx)
0.03 mW Typ.VDD = 3.0 V (ML7001-xx)
•Conforms to ITU-T Companding law
ML7000-01/ML7001-01:m/A-law pin selectableML7000-02/ML7001-02:m-lawML7000-03/ML7001-03:A-law
•Transmission characteristics conform to ITU-T G.714•Short frame sync timing operation•Built-in PLL eliminates a master clock
•Serial data rate:64/96/128/192/200/256/384/512/
768/1024/1536/1544/2048 kHz
•Adjustable transmit gain•Adjustable receive gain
•Built-in reference voltage supply•Package options:
24-pin plastic SOP (SOP24-P-430-1.27-K)(Product name: ML7000-01MA/ML7001-01MA)
(Product name: ML7000-02MA/ML7001-02MA)(Product name: ML7000-03MA/ML7001-03MA)
20-pin plastic SSOP (SSOP20-P-250-0.95-K)(Product name: ML7000-01MB/ML7001-01MB)
(Product name: ML7000-02MB/ML7001-02MB)(Product name: ML7000-03MB/ML7001-03MB)
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ML7000-01/02/03/ML7001-01/02/03
BLOCK DIAGRAM
AIN–AIN+GSX–+RCLPF8thBPFA/DCONV.AUTOZEROTCONTPCMOUTPLLXSYNCBCLKSGCSGSGGENVRGENRTIMD/ACONV.RCONTRSYNC(ALAW)PCMINVFROPWIAOUT–+–+–+–5thLPFPWDPWDLogicAOUT+PDNVDDAGDG2/19
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ML7000-01/02/03/ML7001-01/02/03
PIN CONFIGURATION (TOP VIEW)
SG1AOUT+2AOUT–3NC4PWI5VFRO6NC7VDD8DG9PDN10RSYNC11PCMIN1224SGC23AIN+22AIN–21GSX20NC19NC18(ALAW)*17NC16AG15BCLK14XSYNC13PCMOUTSG1AOUT+2AOUT–3PWI4VFRO5VDD6DG7PDN8RSYNC9PCMIN1020SGC19AIN+18AIN–17GSX16NC15(ALAW)*14AG13BCLK12XSYNC11PCMOUT20-Pin Plastic SSOP24-Pin Plastic SOP*The ALAW pin is only supported by the ML7000-01MA/ML7000-01MB/ML7001-01MA/ML7001-01MB.NC : No connect pin
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PIN FUNCTIONAL DESCRIPTION
AIN+, AIN–, GSX
Transmit analog input and transmit level adjustment.
AIN+ is a non-inverting input to the op-amp; AIN– is an inverting input to the op-amp; GSX isconnected to the output of the op-amp.
The level adjustment should be performed using any of the methods shown below. Duringpower-saving and power-down modes, the GSX output is at AG voltage.
C1Analog inputR1R2GSXAIN–AIN+SG–+R1 : variableR2 > 20 kW
C1 > 1/(2 ¥ 3.14 ¥ 30 ¥ R1)
C2Analog inputR5R4R3AIN+AIN–GSXSG+–R3 > 20 kWR4 > 20 kWR5 > 50 kW
C2 > 1/ (2 ¥ 3.14 ¥ 30 ¥ R5)
AG
Analog ground.VFRO
Receive filter output.
The output signal has an amplitude of 2.4 VPP for ML7000-xx and 2.0 VPP for ML7001-xx aboveand below the signal ground voltage (SG) when the digital signal of +3 dBm0 is input to PCMINand can drive a load of 20 kW or more.
For driving a load of less than 20 kW, connect a resistor of 20 kW or more between the pins VFROand PWI.
During power-saving or power-down mode, the VFRO output is at an SG level.
When adjusting the receive signal on the basis of frequency characteristics, refer to the FrequencyCharacteristics Adjustment Circuit.
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¡ SemiconductorPWI, AOUT+, AOUT–
PWI is connected to the inverting input of the receive driver.
The receive driver output is connected to the AOUT– pin. Therefore, the receive level can beadjusted with the pins VFRO, PWI, and AOUT–. During power-saving or power down-mode,the outputs of AOUT+ and AOUT– are in a high impedance state. The output of AOUT+ isinverted with respect to the output of AOUT–. Since these outputs provide differential drive ofan impedance of 1.2 kW, they can directly be connected to a handset using a piezoelectricearphone or a line transformer. Refer to the application example.
VIVFROPWISG20 kWSG–+AOUT–20 kW–+AOUT+VOZLR6R7R6 > 20 kWZL > 1.2 kWGain = VO/VI = 2 5 R7/R6 £ 2ML7000-01/02/03/ML7001-01/02/03
Receive filterVDD
Power supply for +5 V (ML7000-xx) or +3 V (ML7001-xx)PCMIN
PCM data input.
A serial PCM data input to this pin is converted to an analog signal in synchronization with theRSYNC signal and BCLK signal.
The data rate of PCM is equal to the frequency of the BCLK signal.
PCM signal is shifted in at the falling edge of the BCLK signal and latched into the internalregister when shifted by eight bits.
The start of the PCM data (MSD) is identified at the rising edge of RSYNC.BCLK
Shift clock signal input for the PCMIN and PCMOUT signals.
The frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, or 2048kHz. Setting this signal to logic \"1\" or \"0\" drives both transmit and receive circuits to the powersaving state.
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Receive synchronizing signal input.
Eight required bits are selected from serial PCM signals on the PCMIN pin by the receivesynchronizing signal.
Signals in the receive section are synchronized by this synchronizing signal. This signal must besynchronized in phase with the BCLK. The frequency should be 8 kHz ±50 ppm to guarantee theAC characteristics which are mainly the frequency characteristics of the receive section.
However, if the frequency characteristic of an applied system is not specified exactly, this devicecan operate in the range of 6 to 9 kHz, but the electrical characteristics in this specification are notguaranteed.XSYNC
Transmit synchronizing signal input.
The PCM output signal from the PCMOUT pin is output in synchronization with this signal. Thissynchronizing signal triggers the PLL and synchronizes all timing signals of the transmit section.This synchronizing signal must be synchronized in phase with BCLK.
The frequency should be 8 kHz ±50 ppm to guarantee the AC characteristics which are mainlythe frequency characteristics of the transmit section. However, if the frequency characteristic ofan applied system is not specified exactly, this device operates in the range of 6 to 9 kHz, but theelectrical characteristics in this specification are not guaranteed.
Setting this signal to logic \"1\" or \"0\" drives both transmit and receive circuits to the power savingstate.
ML7000-01/02/03/ML7001-01/02/03
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Ground for the digital signal circuits.
This ground is separate from the analog signal ground AG. The DG pin must be connected to theAG pin on the printed circuit board to make a common analog ground AG.PDN
Power down control signal.
A logic \"0\" level drives both transmit and receive circuits to a power down state.PCMOUT
PCM signal output.
Synchronizing with the rising edge of the BCLK signal, the PCM output signal is output fromMSD in a sequential order.
MSD may be output at the rising edge of the XSYNC signal, based on the timing between BCLKand XSYNC.
This pin is in a high impedance state except during 8-bit PCM output. It is also in a highimpedance state during power saving or power down mode.
A pull-up resistor must be connected to this pin because its output is configured as an open drain.This device is compatible with the ITU-T recommendation on coding law and output codingformat.
The ML7000-03 (A-law) and ML7001-03 (A-law) output the character signal, inverting the evenbits.
PCMIN/PCMOUTInput/Output LevelMSD1100011001100110 011001100110ML7000-02 (m-law)ML7001-02 (m-law)+Full scale+0–0–Full scaleLSD0110MSD1100011010010110 100101101001ML7000-03 (A-law)ML7001-03 (A-law)LSD0110ML7000-01/02/03/ML7001-01/02/03
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Signal ground voltage output.
The output voltage is 1/2 of the power supply voltage.
The output drive current capability is ±300 mA for ML7000-xx and ±200 mA for ML7001-xx.This pin provides the SG level for CODEC peripherals.
This output voltage level is undefined during power-saving or power-down mode.SGC
Used to generate the signal ground voltage level by connecting a bypass capacitor.
Connect a 0.1 mF capacitor with excellent high frequency characteristics between the AG pin andthe SGC pin.ALAW
Control signal input of the companding law selection.
Only the ML7000-01MA/ML7000-01MB/ML7001-01MA/ML7001-01MB have this pin. TheCODEC will operate in the m-law when this pin is at a logic \"0\" level and the CODEC will operatein the A-law when this pin is at a logic \"1\" level. The CODEC operates in the m-law if the pin isleft open, since the pin is internally pulled down.
ML7000-01/02/03/ML7001-01/02/03
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ML7000-01/02/03/ML7001-01/02/03
ABSOLUTE MAXIMUM RATINGS
ParameterPower Supply VoltageAnalog Input VoltageDigital Input VoltageSymbolVDDVAINVDINCondition———Rating–0.3 to +7–0.3 to VDD + 0.3–0.3 to VDD + 0.3UnitVVVRECOMMENDED OPERATING CONDITIONS
ParameterPower Supply VoltageOperating TemperatureAnalog Input VoltageHigh Level Input VoltageLow Level Input VoltageSymbolVDDTaVAINVIHVILCondition——Connect AIN– and GSXMin.4.752.70–30——2.2XSYNC, RSYNC, BCLK,PCMIN, PDN, ALAW0.45¥VDD00BCLKTyp.5.003.00+25——————Max.5.253.30+852.41.2VDDVDD0.80.16¥VDDUnitV°CVPPVV64, 96, 128, 192, 200, 256, Clock FrequencyFC384, 512, 768, 1024, 1536,1544, 2048Sync Pulse FrequencyClock Duty RatioDigital Input Rise TimeDigital Input Fall TimeTransmit Sync Pulse Setting TimeXSYNC Setup TimeXSYNC Hold TimeReceive Sync Pulse Setting TimeRSYNC Setup TimeRSYNC Hold TimePCMIN Setup TimePCMIN Hold TimeDigital Output LoadAnalog Input Allowable DC OffsetAllowable Jitter WidthFSDCtlrtlftCXtXCtXStXHtCRtRCtRStRHtDStDHRDLCDLVoff—XSYNC, RSYNC (–40 to +75 °C)BCLKXSYNC, RSYNC, BCLK,PCMIN, PDNBCLKÆXSYNC, See Fig. 1XSYNCÆBCLK, See Fig. 1——BCLKÆRSYNC, See Fig. 1RSYNCÆBCLK, See Fig. 1————Pull-up resistor—Transmit gain stage, Gain = 0 dBTransmit gain stage, Gain = +20 dBXSYNC, RSYNC, BCLK6.06.040——505050505050505050500.5—–10–100—8.08.050—————————————————9.010.0605050———————————100+10+1001000kHz%nsnsnsnsnsnsnsnsnsnsnsnskWpFmVmVnskHzValues above the dotted line are for ML7000-xx; those below, for ML7001-xx.
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ML7000-01/02/03/ML7001-01/02/03
ELECTRICAL CHARACTERISTICS
DC and Digital Interface Characteristics
(ML7001-xx: VDD = 2.7 V to 3.3 V, Ta = –30 to +85°C)(ML7000-xx: VDD = +5.0 V ±5%, Ta = –30 to +85°C)ParameterSymbolIDD1Power Supply CurrentIDD2IDD3High Level Input VoltageLow Level Input VoltageHigh Level Input Leakage CurrentHigh Level Input Leakage CurrentLow Level Input Leakage CurrentDigital Output Low VoltageDigital Output Leakage CurrentInput CapacitanceVIHVILIIHIIH2IILVOLIOCINALAW—Pull-up resistor = 500 W——No signalXSYNC Æ OFFPower-down mode, PDN = 0,BCLK OFF———ConditionOperating modeVDD = 5.0 VVDD = 3.0 VMin.—————2.20.45¥VDD0.00.0———0.0——Typ.5.06.51.52.00.01———————0.2—5Max.12.010.04.08.00.05VDDVDD0.80.16¥VDD2.030.00.50.410—UnitmAmAmAVVmAmAmAVmApFPower-saving mode, PDN = 1,Values above the dotted line are for ML7000-xx; those below, for ML7001-xx.
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Transmit Analog Interface Characteristics
ParameterInput ResistanceOutput Load ResistanceOutput Load CapacitanceOutput AmplitudeOffset VoltageSymbolRINXRLGXCLGXVOGXVOSGXGain = 1ML7000-01/02/03/ML7001-01/02/03
(ML7001-xx: VDD = 2.7 V to 3.3 V, Ta = –30 to +85°C)(ML7000-xx: VDD = +5.0 V ±5%, Ta = –30 to +85°C)Min.1020—–1.2–0.7–20Typ.——————Max.——30+1.2+0.7+20UnitMWkWpFV0pmVConditionAIN+, AIN–GSX with respect to SGValues above the dotted line are for ML7000-xx; those below, for ML7001-xx.
Receive Analog Interface Characteristics
(ML7001-xx: VDD = 2.7 V to 3.3 V, Ta = –30 to +85°C)(ML7000-xx: VDD = +5.0 V ±5%, Ta = –30 to +85°C)ParameterInput ResistanceOutput Load ResistanceSymbolRINPWPWIRLVFRLAOCLVFCLAOVOVFOutput AmplitudeVOAOVFRO with respect to SGAOUT+, AOUT– (each) withrespect to SGVFROAOUT+, AOUT–VFRO, RL = 20 kW withrespect to SGAOUT+, AOUT–, RL = 0.6 kWwith respect to SGAOUT+, AOUT–, Gain = 1 withrespect to SGConditionMin.10200.6——–1.2–1.0–1.3–1.0–100–100Typ.———————————Max.———3050+1.2+1.0+1.3+1.0+100+100mVmVV0pUnitMWkWkWpFpFOutput Load CapacitanceVOSVFVFRO with respect to SGOffset VoltageVOSAOValues above the dotted line are for ML7000-xx; those below, for ML7001-xx.
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ML7000-01/02/03/ML7001-01/02/03
(ML7001-xx: FS = 8 kHz, VDD = 2.7 V to 3.3 V, Ta = –30 to +85°C)(ML7000-xx: FS = 8 kHz, VDD = +5.0 V ±5%, Ta = –30 to +85°C)SymbolLoss T1Loss T2Loss T3Loss T4Loss T5Loss T6Loss R1Loss R2Freq.(Hz)603001020202030003400300102020203000340030–301020SD T4SD T5SD R1SD R2SD R3–40–4530–301020SD R4SD R5GT T1GT T2–40–453–101020–40–50–553–101020–40–50–55–0.3–0.6–1.2–0.3–0.6–1.2–0.3*1*10–0.15–0.150353535.034.026.026.024.0—363636.035.025.026.025.0—–0.30LevelCondition(dBm0)Min.20–0.15–0.15–0.150–0.15Typ.26+0.07Reference–0.04+0.070.4–0.03Reference0.00+0.050.54434138.038.031.030.025.025.0434140.040.032.032.027.027.0+0.01Reference–0.05–0.05–0.08–0.06Reference+0.08+0.12+0.15+0.3+0.6+1.2dB+0.3+0.6+1.2+0.3dB+0.2+0.20.8————————————————+0.3dBdBdB+0.2+0.20.8+0.2Max.—+0.2dBUnitParameterTransmit Frequency ResponseReceive Frequency ResponseLoss R3Loss R4Loss R5SD T1SD T2SD T3Transmit Signal to Distortion RatioReceive Signal to Distortion RatioTransmit Gain TrackingGT T3GT T4GT T5GT R1GT R2Receive Gain TrackingGT R3GT R4GT R5*1Psophometric filter is used.
Values above the dotted line are for ML7000-xx; those below, for ML7001-xx.
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AC Characteristics (Continued)
ML7000-01/02/03/ML7001-01/02/03
(ML7001-xx: FS = 8 kHz, VDD = 2.7 V to 3.3 V, Ta = –30 to +85°C)(ML7000-xx: FS = 8 kHz, VDD = +5.0 V ±5%, Ta = –30 to +85°C)Freq.(Hz)——
LevelCondition(dBm0)
AIN = SG—
*1 *2—
*1 *2VDD = 5.0 V,Min.————0.580.3380.580.483*3–0.2–0.2———
0
*4
—————
0
*4
———
0
TRANS Æ RECVRECV Æ TRANSParameterSymbolNidle TTyp.–73.0–69.5–78.0–75.00.60070.350.60070.5———0.190.110.020.050.070.000.000.000.090.12–85–76
Max.–66.0–65.0–71.0–65.00.6220.3620.6220.5180.20.20.60.750.350.1250.1250.750.750.350.1250.1250.75–75–70
Unit
Idle Channel Noise
Nidle RdBm0p
AV T
1020
Absolute Level (Initial Difference)
AV R
Absolute Level 0
Ta = 25°CVDD = 3.0 V,Ta = 25°C*3Vrms
AV TtVDD = 5 V ±5%, Ta = –30 to 85°CA to A
(Deviation of Temperature and Power)AV RtVDD = 2.7 to 3.3 V, Ta = –30 to 85°C*3Absolute Delay
TdtGD T1tGD T2Transmit Group Delay
tGD T3tGD T4tGD T5tGD R1tGD R2Receive Group Delay
tGD R3tGD R4tGD R5Crosstalk Attenuation
CR TCR R
10205006001000260028005006001000260028001020
0
BCLK= 64 kHzdB
ms
ms
ms
——
dB
*1*2*3*4Psophometric filter is used.Input \"0\" code to PCMIN.
AVR is defined at VFRO output.
With respect to minimum value of the group delay distortion.
Values above the dotted line are for ML7000-xx; those below, for ML7001-xx.
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AC Characteristics (Continued)
(ML7001-xx: FS = 8 kHz, VDD = 2.7 V to 3.3 V, Ta = –30 to +85°C)(ML7000-xx: FS = 8 kHz, VDD = +5.0 V ±5%, Ta = –30 to +85°C)ParameterDiscriminationOut-of-band SpuriousIntermodulation DistortionPower Supply Noise Rejection RatioDigital Output Delay TimeSymbolFreq.LevelCondition(Hz)(dBm0)0 to4.6 kHz toDIS04000 Hz72 kHzSIMDPSR TPSR RtXD1tXD2300 to3400fa = 470fd = 3200 to50 kHz0–450 mVPP4.6 kHz to100 kHz2fa – fbMeasured inband *5Min.30———2020Typ.32–37.5–5230——Max.—–35–35—200200UnitdBdBm0dBm0dBnsML7000-01/02/03/ML7001-01/02/03
CL = 100 pF + 1 LSTTLPull-up resistor = 500 W*5Measured under idle channel noise.
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ML7000-01/02/03/ML7001-01/02/03
TIMING DIAGRAM
PCM Data Input/Output Timing
Transmit TimingBCLKtXStXHXSYNCtCXtXCtXD1PCMOUTMSD123456789101112tXD2D2D3D4D5D6D7D8Receive TimingBCLKtRStRHRSYNCtCRtRCtDSPCMINMSD123456789101112tDHD4D5D6D7D8D2D3Figure 1 Basic Timing
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ML7000-01/02/03/ML7001-01/02/03
APPLICATION CIRCUIT
+ 5V0.1 mF51 kWML7000-01AIN–600:600600 WGSXAIN+600:600300 W300 WSGAOUT+ALAWAOUT–PWI51 kW0.1 mF10 mF+1 kWPCM signal output8 kHz SYNC signal inputPCMOUTXSYNCRSYNCBCLKPCMINPCM shift clock inputPCM signal inputControl of companding law1: A-law0: m-lawVFROSGCDGAGPDNPower down control input1: Normal operation0: Power down0 V+5 V0 to 20 W1 mFVDD+3 V0.1 mF51 kWML7001-01AIN–600:600600 WGSXAIN+600:600300 W300 WSGAOUT+ALAWAOUT–PWI51 kW0.1 mF10 mF+1 kWPCM signal output8 kHz SYNC signal inputPCMOUTXSYNCRSYNCBCLKPCMINPCM shift clock inputPCM signal inputControl of companding law1: A-law0: m-lawVFROSGCDGAGPDNPower down control input1: Normal operation0: Power down0 V+3 V0 to 20 W1 mFVDD16/19
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ML7000-01/02/03/ML7001-01/02/03
NOTES ON USE
•To ensure proper electrical characteristics, use bypass capacitors with excellent high frequencycharacteristics for the power supply and keep them as close as possible to the device pins.•Connect the AG pin and the DG pin as closely as possible. Connect to the system ground withlow impedance.•Mount the device directly on the board when mounted on PCBs. Do not use IC sockets. If theuse of IC socket is unavoidable, use the short lead type socket.•When mounted on a frame, use electromagnetic shielding if any electromagnetic wavesources such as power supply transformers surrounds the device.•Keep the voltage on the VDD pin not lower than –0.3 V even instantaneously to avoid latch-up that may otherwise occur when power is turned on.•Use a low noise (particularly, low level type of high frequency spike noise or pulse noise)power supply to avoid erroneous operation and the degradation of the characteristics of thesedevices.
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ML7000-01/02/03/ML7001-01/02/03
PACKAGE DIMENSIONS
(Unit : mm)SOP24-P-430-1.27-KMirror finishPackage materialLead frame materialPin treatmentSolder plate thicknessPackage weight (g)Epoxy resin42 alloySolder plating5 mm or more0.58 TYP.Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, whichare very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for theproduct name, package name, pin number, package code and desired mounting conditions(reflow method, temperature and times).
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ML7000-01/02/03/ML7001-01/02/03
(Unit : mm)SSOP20-P-250-0.95-KMirror finishPackage materialLead frame materialPin treatmentSolder plate thicknessPackage weight (g)Epoxy resin42 alloySolder plating5 mm or more0.18 TYP.Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, whichare very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for theproduct name, package name, pin number, package code and desired mounting conditions(reflow method, temperature and times).
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