专利名称：METHOD AND CIRCUIT FOR THE
DETECTION OF SOLDER-JOINT FAILURES INA DIGITAL ELECTRONIC PACKAGE
发明人：VERMEIRE, Bert,HOFMEISTER,
James,SPUHLER, Philipp
申请号：EP06734539.7申请日：20060208公开号：EP1853931A2公开日：20071114
摘要：The solder-joint integrity of digital electronic packages, such as FPGAs (120) ormicrocontrollers that have internally connected input /output buffers (146a/b, 148a/b), isevaluated by applying a time-varying voltage through one or more solder- joint networks(153a) to charge a charge- storage component (156). Each network includes an I/O buffer(146a) on the die (138) in the package and a solder-joint connection (124), typically one ormore such connections inside the package and between the package and a board. Thetime constant for charging the component is proportional to the resistance of thesolder- joint network, hence the voltage measured across the charge-storagecomponent is an indicator of the integrity of the solder-joint network.
申请人：Ridgetop Group, Inc.
地址：6595 N. Oracle Road, Suite 153b Tuscon AZ 85704 US
国籍：US
代理机构：Blood, Marlon
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