专利名称：Interlocked on-chip ecc system发明人：Fifield, John Atkinson申请号：EP91103123.5申请日：19910301公开号：EP0452649B1公开日：19960619
摘要：An interlocked on-chip ECC system for DRAMs wherein performancedegradations due to on-chip ECC are minimized without compromising accurate ECCoperations. Several interlocks used in the system insure that the data thereto is valid atcertain critical stages. The remainder of the system is allowed to run on a self-timed basisto maximize speed. For example, a dummy data line (DDL) is used to signal the ECC (30)when data from the DRAM arrays (10) is valid during a fetch operation; the same dummydata line (DDL) also signals the DRAM arrays (10) when the data from the ECC (30) is validduring a write-back operation.
申请人：IBM
地址：US
国籍：US
代理机构：Jost, Ottokarl, Dipl.-Ing.
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