Table 16:DLL Signals
Mode Support
SignalCLKINCLKFBCLK0CLK90CLK180CLK270CLK2XCLK2X180CLKDV
DirectionInputInputOutputOutputOutputOutputOutputOutputOutput
Accepts original clock signal.
Description
Low Frequency
YesYesYesYesYesYesYesYesYes
High Frequency
YesYesYesNoYesNoNoNoYes
Accepts either CLK0 or CLK2X as feed back signal. (Set CLK_FEEDBACK attribute accordingly).
Generates clock signal with same frequency and phase as CLKIN.
Generates clock signal with same frequency as CLKIN, only phase-shifted 90°.Generates clock signal with same frequency as CLKIN, only phase-shifted 180°.Generates clock signal with same frequency as CLKIN, only phase-shifted 270°.Generates clock signal with same phase as CLKIN, only twice the frequency.Generates clock signal with twice the frequency of CLKIN, phase-shifted 180° with respect to CLKIN.
Divides the CLKIN frequency by CLKDV_DIVIDE value to generate lower frequency clock signal that is phase-aligned to CLKIN.
The clock signal supplied to the CLKIN input serves as a reference waveform, with which the DLL seeks to align the
feedback signal at the CLKFB input. When eliminating clock skew, the common approach to using the DLL is as follows: The CLK0 signal is passed through the clock distribution network to all the registers it synchronizes. These registers are either internal or external to the FPGA. After passing through the clock distribution network, the clock signal returns to the DLL via a feedback line called CLKFB. The control block inside the DLL measures the phase error between CLKFB and CLKIN. This phase error is a measure of the clock skew that the clock distribution network introduces. The control block activates the appropriate number of delay elements to cancel out the clock skew. Once the DLL has brought the CLK0 signal in phase with the CLKIN signal, it asserts the LOCKED output, indicating a “lock” on to the CLKIN signal.
DLL Attributes and Related Functions
A number of different functional options can be set for the DLL component through the use of the attributes described in Table17. Each attribute is described in detail in the sections that follow:Table 17:DLL Attributes
Attribute
CLK_FEEDBACK
DLL_FREQUENCY_MODE CLKIN_DIVIDE_BY_2CLKDV_DIVIDE
Description
Chooses between High Frequency and Low Frequency modesHalves the frequency of the CLKIN signal just as it enters the DCM Selects constant used to divide the CLKIN input frequency to generate the CLKDV output frequency
Enables 50% duty cycle correction for the CLK0, CLK90, CLK180, and CLK270 outputs
Values
LOW, HIGH TRUE, FALSE
1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6.0, 6.5, 7.0, 7.5, 8, 9, 10, 11, 12, 13, 14, 15, and 16.TRUE, FALSE
Chooses either the CLK0 or CLK2X output to drive the CLKFB inputNONE, 1X, 2X
DUTY_CYCLE_CORRECTION
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: DC and Switching Characteristics
Table 59:Switching Characteristics for the DLL (Cont’d)
Speed Grade
Symbol
Description
Frequency Mode /FCLKIN Range
Device
Min
-5Max
2.882.161.200.600.48
-4Min–––––
30.0
UnitsMax
2.882.161.200.600.48
msmsmsmsms
Lock Time
LOCK_DLL
When using the DLL alone: The time from deassertion at the DCM’s Reset input to the rising transition at its
LOCKED output. When the DCM is locked, the CLKIN and CLKFB signals are in phase
18MHz ≤ FCLKIN ≤ 30MHz30MHz < FCLKIN ≤ 40MHz40MHz < FCLKIN ≤ 50MHz50MHz < FCLKIN ≤ 60MHz
FCLKIN > 60MHz
All–––––
Delay Lines
DCM_TAP
Delay tap resolution
All
All
30.0
60.0
60.0
ps
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: DC and Switching Characteristics
Table 61:Switching Characteristics for the DFS
Speed Grade
Symbol
Output Frequency RangesCLKOUT_FREQ_FX_LFCLKOUT_FREQ_FX_HF
Frequency for the CLKFX and CLKFX180 outputs
LowHigh
AllAll
18210
210326(2)
18210
210307(2)
MHzMHz
Description
Frequency Mode
Device
Min
-5Max
Min
-4Max
Units
Output Clock JitterCLKOUT_PER_JITT_FX
Period jitter at the CLKFX and CLKFX180 outputs
All
All
Note 3Note 3Note 3Note 3
ps
Duty Cycle(4)
CLKOUT_DUTY_CYCLE_FXDuty cycle precision for the CLKFX
and CLKFX180 outputs
All
XC3S50XC3S200XC3S400XC3S1000XC3S1500XC3S2000XC3S4000XC3S5000
––––––––
±100±100±250±400±400±400±400±400
––––––––
±100±100±250±400±400±400±400±400
pspspspspspspsps
Phase AlignmentCLKOUT_PHASE
Phase offset between the DFS output and the CLK0 output
All
All
–
±300
–
±300
ps
Lock TimeLOCK_DLL_FX
When using the DFS in conjunction with the DLL: The time from deassertion at the DCM’s Reset input to the rising transition at its LOCKED output. When the DCM is locked, the CLKIN and CLKFB signals are in phase.
When using the DFS without the DLL: The time from deassertion at the DCM’s Reset input to the rising transition at its LOCKED output. By asserting the LOCKED signal, the DFS indicates valid CLKFX and CLKFX180 signals.
All
All
–
10.0
–
10.0
ms
LOCK_FXAllAll–10.0–10.0ms
Notes:
1.2.3.4.5.
The numbers in this table are based on the operating conditions set forth in Table32 and Table60.
Mask revisions prior to the E mask revision have a CLKOUT_FREQ_FX_HF max of 280 MHz. See Mask and Fab Revisions, page58.
Use the DCM Clocking Wizard in the ISE software for a Spartan-3 device specific number. Jitter number assumes 150ps of input clock jitter.The CLKFX and CLKFX180 outputs always approximate 50% duty cycles.
DFS specifications apply when either of the DFS outputs (CLKFX or CLKFX180) is in use.
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: DC and Switching Characteristics
Speed Grade
Symbol
Description
Frequency Mode/FCLKIN Range
-5Min1
-4
Max167
Units
Max167
MHz
Min1
Operating Frequency RangesPSCLK_FREQ (FPSCLK)PSCLK_PULSE
Frequency for the PSCLK inputPSCLK pulse width as a percentage of the PSCLK period
Low
Low
Input Pulse Requirements
FCLKIN ≤ 100MHzFCLKIN > 100MHz
40%45%
60%55%
40%45%
60%55%
--
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: Pinout Descriptions
PackageVQ100 / VQG100CP132 / CPG132(1)TQ144 / TQG144PQ208 / PQG208FT256 / FTG256FG320 / FGG320FG456 / FGG456FG676 / FGG676FG900 / FGG900FG1156 / FGG1156(1)
Leads1001321442082563204566769001156
Type
Very-thin Quad Flat PackChip-Scale PackageThin Quad Flat PackQuad Flat Pack
Fine-pitch, Thin Ball Grid ArrayFine-pitch Ball Grid ArrayFine-pitch Ball Grid ArrayFine-pitch Ball Grid ArrayFine-pitch Ball Grid ArrayFine-pitch Ball Grid Array
Maximum
I/O
638997141173221333489633784
Pitch (mm)0.50.50.50.51.01.01.01.01.01.0
Footprint(mm)16 x 168 x 822 x 2230.6 x 30.617 x 1719 x 1923 x 2327 x 2731 x 3135 x 35
Height (mm)1.201.101.604.101.552.002.602.602.602.60
DS099 (v3.1) June 27, 2013Product Specification
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