Table of Content-
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13.
GENERAL DESCRIPTION.........................................................................................................2 FEATURES.................................................................................................................................2 PIN CONFIGURATIONS............................................................................................................3 PIN DESCRIPTION.....................................................................................................................4 BLOCK DIAGRAM......................................................................................................................6 FUNCTIONAL DESCRIPTION...................................................................................................7 ABSOLUTE MAXIMUM RATINGS.............................................................................................8 DC CHARACTERISTICS............................................................................................................8 AC CHARACTERISTICS..........................................................................................................10 TIMING WAVEFORMS.............................................................................................................12 TYPICAL APPLICATION CIRCUITS........................................................................................14 PACKAGE DIMENSIONS.........................................................................................................16 REVISION HISTORY................................................................................................................18
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Publication Release Date: March 7, 2006
Revision A5
W78L32/W78L032A/W78M032A
1. GENERAL DESCRIPTION
The W78L32 microcontroller supplies a wider frequency range and supply voltages than most 8-bit microcontrollers on the market. It is compatible with the industry standard 80C32 microcontroller series.
The W78L32 contains four 8-bit bidirectional parallel ports, three 16-bit timer/counters and a serial port. These peripherals are supported by a six-source, two-level interrupt capability. There are 256 bytes of RAM, and the device supports ROMless operation for application programs.
The W78L32 microcontroller has two power reduction modes, idle mode and power-down mode, both of which are software selectable. The idle mode turns off the processor clock but allows for continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power consumption. The external clock can be stopped at any time and in any state without affecting the processor.
2. FEATURES
y y y y y y y y y y
Fully static design
Supply voltage of 1.8V to 5.5V
Low power consumption at full supply voltage DC-24 MHz operation
256 bytes of on-chip scratchpad RAM 64K bytes program memory address space 64K bytes data memory address space Four 8-bit bidirectional ports Three 16-bit timer/counters One full duplex serial port
y Boolean processor
y Six-source, two-level interrupt capability y Built-in power management y Packages:
− DIP 40: W78L32-24 − PLCC 44: W78L32P-24 − QFP 44: W78L32F-24
− Lead Free (RoHS) DIP 40: W78L032A24DL, W78M032A24DL − Lead Free (RoHS) PLCC 44: W78L032A24PL, W78M032A24PL − Lead Free (RoHS) PQFP 44: W78L032A24FL, W78M032A24FL
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W78L32/W78L032A/W78M032A
3. PIN CONFIGURATIONS 40-Pin DIP (W78L32)T2, P1.0 T2EX, P1.1P1.2P1.3P1.4P1.5P1.6P1.7RSTRXD, P3.0TXD, P3.1INT0, P3.2INT1, P3.3T0, P3.4T1, P3.5WR, P3.6RD, P3.7XTAL2XTAL1VSS12345678910111213141516171819204039383736353433323130292827262524232221VDDP0.0, AD0P0.1, AD1P0.2, AD2P0.3, AD3P0.4, AD4P0.5, AD5P0.6, AD6P0.7, AD7EAALEPSENP2.7, A15P2.6, A14P2.5, A13P2.4, A12P2.3, A11P2.2, A10P2.1, A9P2.0, A844-Pin PLCC (W78L32P)44-Pin QFP (W78L32F)T2EX,PPPP1111....4321T2EX,PPPP1111....4321ATD20,,PP1V0.ND.0CD0AD1,P0.1AD2,P0.2AD3,P0.312T2,P1V.ND0CDAD0,P0.0AD1,P0.1AD2,P0.2AD3,P0.3P1.5P1.6P1.7RSTRXD, P3.0NCTXD, P3.1INT0, P3.2INT1, P3.3T0, P3.4T1, P3.56543214443424140739838937103611351234133314321531163017291819202122232425262728P3.6,/WRP3.7,/RDXTAL2XVNPTSC2AS.L01,A8P2.1,A9P2.2,A10P2.3,A11P2.4,A12P0.4, AD4P0.5, AD5P0.6, AD6P0.7, AD7EANCALEPSENP2.7, A15P2.6, A14P2.5, A13P1.5P1.6P1.7RSTRXD, P3.0NCTXD, P3.1INT0, P3.2INT1, P3.3T0, P3.4T1, P3.544434241403938373635343332313304295286277268925102411231213141516171819202122P3.6,/WRP3.7,/RDXTAL2XVNPTSC2AS.L01,A8P2.1,A9P2.2,A10P2.3,A11P2.4,A12P0.4, AD4P0.5, AD5P0.6, AD6P0.7, AD7EANCALEPSENP2.7, A15P2.6, A14P2.5, A13 - 3 -
Publication Release Date: March 7, 2006
Revision A5
W78L32/W78L032A/W78M032A
4. PIN DESCRIPTION
P0.0−P0.7
Port 0, Bits 0 through 7. Port 0 is a bidirectional I/O port. This port also provides a multiplexed low order address/data bus during accesses to external memory.
P1.0−P1.7
Port 1, Bits 0 through 7. Port 1 is a bidirectional I/O port with internal pull-ups. Pins P1.0 and P1.1 also serve as T2 (Timer 2 external input) and T2EX (Timer 2 capture/reload trigger), respectively.
P2.0−P2.7
Port 2, Bits 0 through 7. Port 2 is a bidirectional I/O port with internal pull-ups. This port also provides the upper address bits for accesses to external memory.
P3.0−P3.7
Port 3, Bits 0 through 7. Port 3 is a bidirectional I/O port with internal pull-ups. All bits have alternate functions, which are described below:
PIN ALTERNATE FUNCTION P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 RXD Serial Receive Data TXD Serial Transmit Data INT0 External Interrupt 0 INT1 External Interrupt 1 T0 Timer 0 Input T1 Timer 1 Input WR Data Write Strobe RD Data Read Strobe EA
External Address Input, active low. This pin forces the processor to execute out of external ROM. This
pin should be kept low for all W78L32 operations.
RST
Reset Input, active high. This pin resets the processor. It must be kept high for at least two machine cycles in order to be recognized by the processor.
ALE
Address Latch Enable Output, active high. ALE is used to enable the address latch that separates the address from the data on Port 0. ALE runs at 1/6th of the oscillator frequency. A single ALE pulse is skipped during external data memory accesses. ALE goes to a high state during reset with a weak pull-up.
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W78L32/W78L032A/W78M032A
PSEN
Program Store Enable Output, active low. PSEN enables the external ROM onto the Port 0 address/data bus during fetch and MOVC operations. PSEN goes to a high state during reset with a weak pull-up.
XTAL1
Crystal 1. This is the crystal oscillator input. This pin may be driven by an external clock.
XTAL2
Crystal 2. This is the crystal oscillator output. It is the inversion of XTAL1.
VSS, VDD
Power Supplies. These are the chip ground and positive supplies.
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Publication Release Date: March 7, 2006
Revision A5
W78L32/W78L032A/W78M032A
5. BLOCK DIAGRAM
RAM256BytesSFRPort 0Port 1AlternateTimer 2CPUData BusPort 2Port 3AlternateCORESerialPortTimer 0InterruptTimer 1INT 0INT 1
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W78L32/W78L032A/W78M032A
6. FUNCTIONAL DESCRIPTION
The W78L32 architecture consists of a core controller surrounded by various registers, four general purpose I/O ports, 256 bytes of RAM, three timer/counters, and a serial port. The processor supports 111 different instruction and references both a 64K program address space and a 64K data storage space.
Timers 0, 1, and 2
Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0, TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide control functions for timers 0, 1. The T2CON register provides control functions for Timer 2. RCAP2H and RCAP2L are used as reload/capture registers for Timer 2.
The operations of Timer 0 and Timer 1 are the same as in the W78C31. Timer 2 is a special feature of the W78L32: it is a 16-bit timer/counter that is configured and controlled by the T2CON register. Like Timers 0 and 1, Timer 2 can operate as either an external event counter or as an internal timer, depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating modes: capture, auto-reload, and baud rate generator. The clock speed at capture or auto-reload mode is the same as that of Timers 0 and 1.
Clock
The W78L32 is designed to be used with either a crystal oscillator or an external clock. Internally, the clock is divided by two before it is used. This makes the W78L32 relatively insensitive to duty cycle variations in the clock.
Crystal Oscillator
The W78L32 incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from each pin to ground, and a resistor must also be connected from XTAL1 to XTAL2 to provide a DC bias when the crystal frequency is above 24 MHz.
External Clock
An external clock should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The XTAL1 input is a CMOS-type input, as required by the crystal oscillator. As a result, the external clock signal should have an input one level of greater than 3.5 volts when VDD = 5V.
Power Management
Idle Mode
The idle mode is entered by setting the IDL bit in the PCON register. In the idle mode, the internal clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The processor will exit idle mode when either an interrupt or a reset occurs.
Power-down Mode
When the PD bit of the PCON register is set, the processor enters the power-down mode. In this mode all of the clocks, including the oscillator are stopped. The only way to exit power-down mode is by a reset.
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Publication Release Date: March 7, 2006
Revision A5
W78L32/W78L032A/W78M032A
Reset
The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to deglitch the reset line when the W78L32 is used with an external RC network. The reset logic also has a special glitch removal circuit that ignores glitches on the reset line. During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit 4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset.
7. ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL MIN. MAX. UNIT DC Power Supply Input Voltage
Operating Temperature Storage Temperature
VCC−VSS VIN TA TST
-0.3 +7.0 V VSS -0.3 VCC +0.3 V 0 70 °C -55 +150 °C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
8. DC CHARACTERISTICS
(VDD−VSS = 5V ±10%, TA = 25°C, Fosc = 20 MHz, unless otherwise specified.) PARAMETER SYM.PECIFICATION MIN. MAX. UNIT TEST CONDITIONS Operating Voltage Operating Current Idle Current Power Down Current Input Current P1, P2, P3 Input Current RST Input Leakage Current P0, EA Logic 1 to 0 Transition Current P1, P2, P3 VDD IDD IIDLE IPWDN IIN1 IIN2 ILK 1.8 5.5 V - - 20 3 mA mA No load, VDD = 5.5V, 20 MHzNo load, VDD = 2.0V, 16 MHz- 6 mA VDD = 5.5V, Fosc = 20 MHz- 1.5 mA VDD = 2.0V, Fosc =16 MHz - 50 µA - 20 µA -50 +10 µA -10 +300 µA -10 +10 µA VDD = 5.5V, Fosc = 20 MHzVDD = 2.0V, Fosc = 16 MHzVDD = 5.5V VIN = 0V or VDD VDD = 5.5V 0 < VIN < VDD VDD = 5.5V 0V < VIN < VDD VDD = 5.5V VIN = 2.0V ITL [*4]-500 - µA - 8 -
W78L32/W78L032A/W78M032A
DC Characteristics, continued
PECIFICATION PARAMETER SYM. UNITMIN. MAX. TEST CONDITIONS Input Low Voltage P0, P1, P2, P3, EA Input Low Voltage RST Input Low Voltage XTAL1 [*4] Input High Voltage P0, P1, P2, P3, EA Input High Voltage RST Input High Voltage XTAL1 [*4] Output Low Voltage P1, P2, P3 Output Low Voltage P0, ALE, PSEN [*3] Sink Current P1, P2, P3 Sink Current P0, ALE, PSEN Output High Voltage P1, P2, P3 Output High Voltage P0, ALE, PSEN [*3] Source Current P1, P2, P3 Source Current P0, ALE, PSEN Notes:
VIL1 VIL2 VIL3 VIH1 VIH2 VIH3 VOL1 VOL2 ISK1 ISK2 VOH1 VOH2 ISR1 ISR2 0 0.8 V 0 0.5 V 0 0.8 V 0 0.3 V 0 0.8 V 0 0.6 V 2.4 VDD +0.21.4 VDD +0.23.5 VDD +0.21.7 VDD +0.23.5 VDD +0.21.6 VDD +0.2VDD = 4.5V VDD = 2.0V VDD = 4.5V VDD = 2.0V VDD = 4.5V VDD = 2.0V V VDD = 5.5V V VDD = 2.0V V VDD = 5.5V V VDD = 2.0V V VDD = 5.5V V VDD = 2.0V - 0.45 V VDD = 4.5V, IOL = +2 mA - 0.25 V VDD = 2.0V, IOL = +1 mA - 0.45 V VDD = 4.5V, IOL = +4 mA - 0.25 V VDD = 2.0V, IOL = +2 mA 4 9 mA VDD = 4.5V, Vin = 0.45V 1.8 5.4 mA VDD = 2.0V, Vin = 0.45V 8 16 mA VDD = 4.5V, Vin = 0.45V 4.5 9 mA VDD = 2.0V, Vin = 0.45V 2.4 - V VDD = 4.5V, IOH = -100 µA 1.4 - V VDD = 2.0V, IOH = -8 µA 2.4 - V VDD = 4.5V, IOH = -400 µA 1.4 - V VDD = 2.0V, IOH = -200 µA -100 -250 µA -12 -30 µA VDD = 4.5V,Vin = 2.4V VDD = 2.0V,Vin = 1.4V -8 -16 mA VDD = 4.5V,Vin = 2.4V -1.4 -2.4 mA VDD = 2.0V,Vin = 1.4V *1. RST pin is a Schmitt trigger input.
*3. P0, ALE and /PSEN are tested in the external access mode. *4. XTAL1 is a CMOS input.
*5. Pins of P1, P2, P3 can source a transition current when they are being externally driven from 1 to 0.
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Publication Release Date: March 7, 2006
Revision A5
W78L32/W78L032A/W78M032A
9. AC CHARACTERISTICS
The AC specifications are a function of the particular process used to manufacture the part, the ratings of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the specifications can be expressed in terms of multiple input clock periods (TCP), and actual parts will usually experience less than a ±20 nS variation. The numbers below represent the performance expected from a 0.5 micron CMOS process when using 2 and 4 mA output buffers.
Clock Input Waveform
XTAL1TCHFOP, TCPTCL PARAMETER SYMBOL MIN. TYP. MAX.
UNIT NOTES
Operating Speed Clock Period Clock High Clock Low FOP TCP TCH TCL 0 - 24 MHz 1 41.7 - - nS 2 20 - - nS 3 20 - - nS 3 Notes:
1. The clock may be stopped indefinitely in either state.
2. The TCP specification is used as a reference in other specifications. 3. There are no duty cycle requirements on the XTAL1 input.
Program Fetch Cycle PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTESAddress Valid to ALE Low Address Hold after ALE Low ALE Low to PSEN Low PSEN Low to Data Valid TAAS TAAH TAPL TPDA TPDH TPDZ TALW TPSW 1 TCP-∆1 TCP-∆1 TCP-∆- - nS 4 - - nS 1, 4 - - nS 4 - - 2 TCPnS 2 0 - 1 TCPnS 3 0 2 TCP-∆3 TCP-∆- 2 TCP3 TCP1 TCP- - nS nS nS 4 4 Data Hold after PSEN High Data Float after PSEN High ALE Pulse Width PSEN Pulse Width Notes:
1. P0.0−P0.7, P2.0−P2.7 remain stable throughout entire memory cycle. 2. Memory access time is 3 TCP.
3. Data have been latched internally prior to PSEN going high. 4. \"∆\" (due to buffer driving delay and wire loading) is 20 nS.
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W78L32/W78L032A/W78M032A
Data Read Cycle
PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTESALE Low to RD Low RD Low to Data Valid TDAR TDDA TDDH TDDZ TDRD 3 TCP-∆- 3 TCP+∆ nS 1, 2 - - 4 TCP nS 1 0 - 2 TCP nS nS nS 2 Data Hold after RD High Data Float after RD High RD Pulse Width 0 - 2 TCP 6 TCP-∆6 TCP- Notes:
1. Data memory access time is 8 TCP.
2. \"∆\" (due to buffer driving delay and wire loading) is 20 nS.
Data Write Cycle PARAMETER SYMBOL MIN. TYP. MAX. UNIT ALE Low to WR Low Data Valid to WR Low Data Hold from WR High WR Pulse Width TDAW TDAD TDWD TDWR 3 TCP-∆ 1 TCP-∆ 1 TCP-∆ 6 TCP-∆ - 3 TCP+∆ nS - - nS - - nS 6 TCP - nS Note: \"∆\" (due to buffer driving delay and wire loading) is 20 nS.
Port Access Cycle
PARAMETER SYMBOL MIN. TYP. MAX. UNIT Port Input Setup to ALE Low Port Input Hold from ALE Low Port Output to ALE
TPDS TPDH TPDA
1 TCP 1 TCP
- - nS - - nS 0 - - nS Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to
ALE, since it provides a convenient reference.
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Publication Release Date: March 7, 2006
Revision A5
W78L32/W78L032A/W78M032A
10. TIMING WAVEFORMS
Program Fetch Cycle S1XTAL1TALWALETAPLPSENTPSWTAASPORT 2TAAHPORT 0CodeA0-A7DataA0-A7 CodeA0-A7DataA0-A7TPDATPDH,TPDZS2S3S4S5S6S1S2S3S4S5S6
Data Read Cycle
S4XTAL1ALEPSENPORT 2S5S6S1S2S3S4S5S6S1S2S3A8-A15 A0-A7 DATATDDATDDH,TDDZPORT 0TDARRDTDRD - 12 -
W78L32/W78L032A/W78M032A
Timing Waveforms, continued
Data Write Cycle
S4XTAL1ALE PSENPORT 2PORT 0 WRS5S6S1S2S3S4S5S6S1S2S3A8-A15A0-A7DATA OUTTDADTDWDTDAWTDWR Port Access Cycle
S5XTAL1S6S1ALETPDSPORTINPUTSAMPLETPDHTPDADATA OUT
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Publication Release Date: March 7, 2006
Revision A5
W78L32/W78L032A/W78M032A
11. TYPICAL APPLICATION CIRCUITS
Using External Program Memory and Crystal VDD 31EA10 uCRYSTAL 19XTAL1R 18XTAL2 9RSTINT0INT1T0T1P1.0P1.1P1.2P1.3P1.4P1.5P1.6P1.7W78L328.2 KC1C2P0.0P0.1P0.2P0.3P0.4P0.5P0.6P0.7P2.0P2.1P2.2P2.3P2.4P2.5P2.6P2.739AD038AD137AD236AD335AD434AD533AD632AD72122232425262728A8A9A10A11A12A13A14A15AD0 3AD1 4AD2 7AD3 8AD4 13AD5 14AD6 17AD7 18D0D1D2D3D4D5D6D7Q0Q1Q2Q3Q4Q5Q6Q7 2A0 5A1 6A2 9A312A415A516A619A7 12 13 14 15 1 2 3 4 5 6 7 8 1GNDOC 11G74LS373A0 10A1 9A2 8A3 7A4 6A5 5A6 4A7 3A8 25A9 24A10 21A11 23A12 2A13 26A14 27A15 1A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15O0O1O2O3O4O5O6O71112131516171819AD0AD1AD2AD3AD4AD5AD6AD7RD17WR1629PSEN30ALE11TXD10RXDGND 20CE 22OE27512Figure A
CRYSTAL C1 C2 R 16 MHz 24 MHz
30P 15P
30P 15P
- -
Above table shows the reference values for crystal applications.
Note: C1, C2, R components refer to Figure A.
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W78L32/W78L032A/W78M032A
Typical Application Circuits, continued
Expanded External Data Memory and Oscillator
VDD 31 1910 uOSCILLATOREAXTAL1XTAL2RSTINT0INT1T0T1P1.0P1.1P1.2P1.3P1.4P1.5P1.6P1.7W78L32 188.2 K 9 12 13 14 15 1 2 3 4 5 6 7 8P0.0P0.1P0.2P0.3P0.4P0.5P0.6P0.7P2.0P2.1P2.2P2.3P2.4P2.5P2.6P2.7RDWRPSENALETXDRXD39383736353433322122232425262728171629301110AD0AD1AD2AD3AD4AD5AD6AD7A8A9A10A11A12A13A14AD0 3AD1 4AD2 7AD3 8AD4 13AD5 14AD6 17AD7 18GND 1D0D1D2D3D4D5D6D7Q0Q1Q2Q3Q4Q5Q6Q7 2 5 6 912151619A0A1A2A3A4A5A6A7OC 11G74LS373A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14109876543252421232261A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14CEOEWR20256D0D1D2D3D4D5D6D71112131516171819AD0AD1AD2AD3AD4AD5AD6AD7GND202227Figure B
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Publication Release Date: March 7, 2006
Revision A5
W78L32/W78L032A/W78M032A
12. PACKAGE DIMENSIONS
40-pin DIP Dimension in inchDimension in mmMin.Nom.Max.Min.Nom.Max.0.2100.0100.1500.1550.1600.0160.0180.0220.0480.0500.0540.0080.0100.0142.0552.0700.2543.813.9374.0645.334SymbolD4021E1AA1A2BB1cDEE1e1La0.4060.4570.5591.2191.271.3720.2030.2540.35652.2052.580.5900.6000.61014.98615.2415.4940.5400.5450.55013.7213.8413.970.0900.1000.1102.2860.1200.1300.1403.04801502.542.7943.3023.556151SAA2LBB1e120EcA1eASNotes:0.6300.6500.67016.0016.5117.010.0902.286Base PlaneSeating PlaneaeA1. Dimension D Max. & S include mold flash ortie bar burrs.2. Dimension E1 does not include interlead flash.3. Dimension D & E1 include mold mismatch and.are determined at the mold parting line.4. Dimension B1 does not include dambarprotrusion/intrusion.5. Controlling dimension: Inches.6. General appearance spec. should be based onfinal visual inspection spec.
44-pin PLCC
HDD614440Symbol39Dimension in inchDimension in mmMin.Nom.Max.Min.Nom.Max.0.1850.0200.1450.0260.0160.0080.6480.6480.5900.5900.6800.6800.0900.1500.0280.0180.0100.6530.6530.1550.0320.0220.0140.6580.6580.5083.6830.660.4060.20316.4616.463.810.7110.4570.25416.5916.593.9370.8130.5590.35616.7116.714.6997EHEGE17291828cAA1A2b1bcDEeGDGEHDHELyNotes:0.050BSC0.6300.6300.7000.7000.1100.0041.2714.9914.9917.2717.272.296BSC16.0016.0017.7817.782.7940.100.6100.6100.6900.6900.10015.4915.4917.5317.532.54LA2AθeSeating PlaneGDbb1A1y1. Dimension D & E do not include interleadflash.2. Dimension b1 does not include dambarprotrusion/intrusion.3. Controlling dimension: Inches4. General appearance spec. should be basedon final visual inspection spec. - 16 -
W78L32/W78L032A/W78M032A
Package Dimensions, continued
44-pin QFP HDD4434Dimension in inchDimension in mmSymbolMin.Nom.Max.Min.Nom.Max.133EHE1112eb22AA1A2bcDEeHDHELL1yθNotes:c --- --- ---0.02 ---0.051.900.25 ---0.252.050.35 ---0.52.200.450.0020.010.0750.0810.0870.010.0140.0180.0040.0060.0100.3900.3940.3980.3900.3940.3980.0250.0310.0360.1010.1520.2549.99.90.63510.0010.000.8013.210.110.10.95213.4513.450.951.9050.08070.5100.5200.53012.950.5100.5200.53012.9513.20.0250.0310.0370.650.81.60.0510.0630.0751.2950.00307A2AA1yθLL1Detail FSeating PlaneSee Detail F1. Dimension D & E do not include interleadflash.2. Dimension b does not include dambarprotrusion/intrusion.3. Controlling dimension: Millimeter4. General appearance spec. should be basedon final visual inspection spec.
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Publication Release Date: March 7, 2006
Revision A5
W78L32/W78L032A/W78M032A
13. REVISION HISTORY
VERSION DATE PAGE REASONS FOR CHANGE
A2 October 2000 - A3 A4 A5
April 20, 2005 December 21, 2005 March 7, 2006
16 2 2
Add Important Notice Add lead-free(RoHS) parts Add 2nd lead-free(RoHS) parts
Important Notice
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7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033TEL: 81-45-4781881FAX: 81-45-4781800
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong KongTEL: 852-27513100FAX: 852-27552064
9F, No.480, Rueiguang Rd.,Neihu District, Taipei, 114,Taiwan, R.O.C.
TEL: 886-2-8177-7168FAX: 886-2-8751-3579
Please note that all data and specifications are subject to change without notice.
All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
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