MEMORY存储芯片MT46H8M32LFB5-6IT中文规格书

Electrical Characteristics – AC and DC Single-Ended Input

Measurement Levels

Table 96: CT Type-B Input Levels

ParameterCTipB AC input high voltageCTipB DC input high voltageCTipB DC input low voltageCTipB AC input low voltageCTipB falling timeCTipB rising timeNotes:

SymbolVIH(AC)VIH(DC)VIL(DC)VIL(AC)tF_CTipBtR_CTipBMinVREF + 300VREF + 200VSSVSS11––MaxVDD11VDDVREF - 200VREF - 30055UnitVVVVnsnsNote2, 32, 32, 32, 3221.Refer to Overshoot and Undershoot Specifications.

2.CT Type-B inputs: DML_n/DBIL_n, DMU_n/DBIU_n and DM_n/DBI_n.3.VREFDQ should be 0.5 × VDD

Figure 218: CT Type-B Input Slew Rate Definition

VIH(AC)_CTipBminVIH(DC)_CTipBminVREFDQVIL(DC)_CTipBmaxVIL(AC)_CTipBmaxtF_CTipBtR_CTipBTable 97: CT Type-C Input Levels (CMOS)

ParameterCTipC AC input high voltageCTipC DC input high voltageCTipC DC input low voltageCTipC AC input low voltageCTipC falling timeCTipC rising timeNotes:

SymbolVIH(AC)_CTipCVIH(DC)_CTipCVIL(DC)_CTipCVIL(AC)_CTipCtF_CTipCtR_CTipCMin0.8 × VDD0.7 × VDDVSSVSS1––MaxVDD1VDD0.3 × VDD0.2 × VDD1 01 0UnitVVVVnsnsNote2222221.Refer to Overshoot and Undershoot Specifications.2.CT Type-C inputs: Alert_n.

8Gb: x4, x8, x16 DDR4 SDRAM

Electrical Characteristics – AC and DC Single-Ended Input

Measurement Levels

Figure 219: CT Type-C Input Slew Rate Definition

VIH(AC)_TENminVIH(DC)_TENmin

VIL(DC)_TENminVIL(AC)_TENmin

tF_TENtR_TENTable 98: CT Type-D Input Levels

ParameterCTipD AC input high voltageCTipD DC input high voltageCTipD DC input low voltageCTipD AC input low voltageRising timeRESET pulse width - after power-upRESET pulse width - during power-upNotes:

SymbolVIH(AC)_CTipDVIH(DC)_CTipDVIL(DC)_CTipDVIL(AC)_CTipDtR_RESETtPW_RESET_StPW_RESET_LMin0.8 × VDD0.7 × VDDVSSVSS–1200MaxVDDVDD0.3 × VDD0.2 × VDD1––UnitVVVVμsμsμsNote421531.After RESET_n is registered LOW, the RESET_n level must be maintained below VIL(DC)_RE-t

SET during PW_RESET, otherwise, the DRAM may not be reset.

2.After RESET_n is registered HIGH, the RESET_n level must be maintained above

VIH(DC)_RESET, otherwise, operation will be uncertain until it is reset by asserting RESET_nsignal LOW.

3.Slope reversal (ring-back) during this level transition from LOW to HIGH should be miti-gated as much as possible.

4.Overshoot should not exceed the VIN values in the Absolute Maximum Ratings table.5.Undershoot should not exceed the VIN values in the Absolute Maximum Ratings table.6.CT Type-D inputs: RESET_n; same requirements as in normal mode.

Figure 220: CT Type-D Input Slew Rate Definition

tPW_RESETVIH(AC)_RESETminVIH(DC)_RESETmin

VIL(DC)_RESETmaxVIL(AC)_RESETmax

tR_RESET8Gb: x4, x8, x16 DDR4 SDRAM

Electrical Characteristics – AC and DC Differential Input Meas-urement Levels

Electrical Characteristics – AC and DC Differential Input MeasurementLevels

Differential Inputs

Figure 221: Differential AC Swing and “Time Exceeding AC-Level” tDVAC

tDVACVIH,diff(AC)min

VIH,diff,min

CK_t, CK_c0.0

VIL,diff,max

VIL,diff(AC)max

Half cycleNotes:

tDVAC

1.Differential signal rising edge from VIL,diff,max to VIH,diff(AC)min must be monotonic slope.2.Differential signal falling edge from IH,diff,min to VIL,diff(AC)max must be monotonic slope.

Table 99: Differential Input Swing Requirements for CK_t, CK_c

DDR4-1600 /1866 / 2133Min150Note 32 ×(VIH(AC)-VREF)MaxNote 3–150Note 3DDR4-2400 /2666Min135Note 32 ×(VIH(AC)-VREF)MaxNote 3-135Note 3DDR4-2933Min125Note 32 ×(VIH(AC)-VREF)MaxNote 3-125Note 3DDR4-3200Min110Note 32 ×(VIH(AC)-VREF)MaxNote 3-110Note 3ParameterDifferential input highDifferential input lowDifferential input high(AC)Sym-bolVIHdiffVILdiffVIH-diff(AC)NotesUnitmVmVV112