FEATURES“Linear in dB” Gain ControlPin Programmable Gain Ranges–11 dB to +31 dB with 90 MHz Bandwidth+9 dB to +51 dB with 9 MHz BandwidthAny Intermediate Range, e.g., –1 dB to +41 dB with30 MHz BandwidthBandwidth Independent of Variable Gain1.3 nV/√Hz Input Noise Spectral Density؎0.5 dB Typical Gain AccuracyMIL-STD-883 Compliant and DESC Versions AvailableAPPLICATIONSRF/IF AGC AmplifierVideo Gain ControlA/D Range ExtensionSignal MeasurementPRODUCT DESCRIPTIONLow Noise, 90MHzVariable-Gain AmplifierAD603*1 V to span the central 40 dB of the gain range. An over- andunder-range of 1 dB is provided whatever the selected range. Thegain-control response time is less than 1µs for a 40 dB change.The differential gain-control interface allows the use of eitherdifferential or single-ended positive or negative control voltages.Several of these amplifiers may be cascaded and their gain-con-trol gains offset to optimize the system S/N ratio.The AD603 can drive a load impedance as low as 100 Ω withlow distortion. For a 500 Ω load in shunt with 5 pF, the totalharmonic distortion for a ±1V sinusoidal output at 10 MHz istypically –60 dBc. The peak specified output is ±2.5 V mini-mum into a 500Ω load, or ±1 V into a 100 Ω load.The AD603 uses a proprietary circuit topology—the X-AMP™.The X-AMP comprises a variable attenuator of 0 dB to –42.14dB followed by a fixed-gain amplifier. Because of theattenuator, the amplifier never has to cope with large inputs andcan use negative feedback to define its (fixed) gain and dynamicperformance. The attenuator has an input resistance of 100 Ω,laser trimmed to ±3%, and comprises a seven-stage R-2R laddernetwork, resulting in an attenuation between tap points of6.021dB. A proprietary interpolation technique provides acontinuous gain-control function which is linear in dB.The AD603A is specified for operation from –40°C to +85°Cand is available in both 8-lead SOIC (R) and 8-lead ceramicDIP (Q). The AD603S is specified for operation from –55°C to+125°C and is available in an 8-lead ceramic DIP (Q). TheAD603 is also available under DESC SMD 5962-94572.The AD603 is a low noise, voltage-controlled amplifier for usein RF and IF AGC systems. It provides accurate, pin selectablegains of –11dB to +31dB with a bandwidth of 90 MHz or+9dB to +51 dB with a bandwidth of 9 MHz. Any intermediategain range may be arranged using one external resistor. Theinput referred noise spectral density is only 1.3nV/√Hz and powerconsumption is 125 mW at the recommended ±5 V supplies.The decibel gain is “linear in dB,” accurately calibrated, andstable over temperature and supply. The gain is controlled at ahigh impedance (50 MΩ), low bias (200 nA) differential input;the scaling is 25 mV/dB, requiring a gain-control voltage of onlyFUNCTIONAL BLOCK DIAGRAMVPOSVNEGGPOSSCALINGREFERENCEPRECISION PASSIVEINPUT ATTENUATORFIXED GAINAMPLIFIERVOUTVGGNEGGAINCONTROLINTERFACEAD6036.44k⍀*FDBK694⍀*0dBVINP–6.02dB–12.04dB–18.06dB–24.08dB–30.1dB–36.12dB–42.14dBR2RR2RR2RR2RR2RR2RRR*NORMAL VALUES20⍀*COMMR = 2R LADDER NETWORK*Patented.X-AMP is a trademark of Analog Devices, Inc.REV.C
Information furnished by Analog Devices is believed to be accurate andreliable. However, no responsibility is assumed by Analog Devices for itsuse, nor for any infringements of patents or other rights of third partieswhich may result from its use. No license is granted by implication orotherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781/329-4700World Wide Web Site: http://www.analog.comFax: 781/326-8703© Analog Devices, Inc., 2000
AD603–SPECIFICATIONSModelParameterINPUT CHARACTERISTICSInput ResistanceInput CapacitanceInput Noise Spectral Density1Noise Figure1 dB Compression PointPeak Input VoltageOUTPUT CHARACTERISTICS–3 dB BandwidthSlew RatePeak Output2Output ImpedanceOutput Short-Circuit CurrentGroup Delay Change vs. GainGroup Delay Change vs. FrequencyDifferential GainDifferential PhaseTotal Harmonic Distortion3rd Order InterceptACCURACYGain AccuracyTMIN to TMAXOutput Offset Voltage3TMIN to TMAXOutput Offset Variation vs. VGTMIN to TMAXGAIN CONTROL INTERFACEGain Scaling FactorTMIN to TMAXGNEG, GPOS Voltage Range4Input Bias CurrentInput Offset CurrentDifferential Input ResistanceResponse RatePOWER SUPPLYSpecified Operating RangeQuiescent CurrentTMIN to TMAX(@ TA = +25؇C, VS = ؎5 V, –500 mV ≤ VG ≤ +500 mV, GNEG = 0 V, –10 dB to +30dB GainRange, RL = 500⍀, and CL = 5 pF, unless otherwise noted.)Min97AD603TypMax10021.38.8–11±1.490275±3.0250±2±20.20.2–6015±0.5؎1±1.52030203040.642+2.0103UnitΩpFnV/√HzdBdBmVMHzV/µsVΩmAnsns%DegreedBcdBmdBdBmVmVmVmVdB/VdB/VVnAnAMΩdB/µsVmAmAConditionsPins 3 to 4Input Short Circuitedf = 10 MHz, Gain = max, RS = 10 Ωf = 10 MHz, Gain = max, RS = 10 Ω±2VOUT = 100 mV rmsRL ≥ 500 ΩRL ≥ 500 Ωf ≤ 10 MHzf = 3 MHz; Full Gain RangeVG = 0 V; f = 1 MHz to 10 MHzf = 10 MHz, VOUT = 1V rmsf = 40 MHz, Gain = max, RS = 50 Ω–500 mV ≤ VG ≤ +500 mVVG = 0V–500 mV ≤ VG ≤ +500 mV±2.539.438–1.2Pins 1 to 2Full 40 dB Gain Change±4.754020010504012.5±6.31720NOTES1Typical open or short-circuited input; noise is lower when system is set to maximum gain and input is short-circuited. This figure includes the effects of both voltageand current noise sources.2Using resistive loads of 500Ω or greater, or with the addition of a 1 kΩ pull-down resistor when driving lower loads.3The dc gain of the main amplifier in the AD603 is ×35.7; thus, an input offset of 100 µV becomes a 3.57 mV output offset.4GNEG and GPOS, gain control, voltage range is guaranteed to be within the range of –VS + 4.2 V to +VS – 3.4 V over the full temperature range of –40°C to +85°C.Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All minand max specifications are guaranteed, although only those shown in boldface are tested on all production units.Specifications subject to change without notice.–2–REV. C
AD603
ABSOLUTE MAXIMUM RATINGS1PIN FUNCTION DESCRIPTIONSSupplyVoltage ±VS . . . . . . . . . . . . . . . . . . . . . . . . . . . .±7.5VInternalVoltage VINP (Pin 3) . . . . . . . . . . . ±2 V Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VS for 10 msGPOS, GNEG (Pins 1, 2) . . . . . . . . . . . . . . . . . . . . . . . ±VSInternal Power Dissipation2 . . . . . . . . . . . . . . . . . . . . 400mWOperating Temperature RangeAD603A . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°CAD603S . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°CStorage Temperature Range . . . . . . . . . . . . –65°C to +150°CLead Temperature Range (Soldering60sec) . . . . . . . .+300°CNOTES1Stresses above those listed under Absolute Maximum Ratings may cause perma-nent damage to the device. This is a stress rating only; functional operation of thedevice at these or any other conditions above those indicated in the operationalsection of this specification is not implied. Exposure to absolute maximum ratingconditions for extended periods may affect device reliability.2Thermal Characteristics:8-Lead SOIC Package: θJA = 155°C/W, θJC = 33°C/W8-Lead Ceramic Package: θJA = 140°C/W, θJC = 15°C/W PinPin 1Pin 2Pin 3Pin 4Pin 5Pin 6Pin 7Pin 8MnemonicGPOSGNEGVINPCOMMFDBKVNEGVOUTVPOSDescriptionGain-Control Input “HI”(Positive Voltage Increases Gain)Gain-Control Input “LO”(Negative Voltage Increases Gain)Amplifier InputAmplifier GroundConnection to Feedback NetworkNegative Supply InputAmplifier OutputPositive Supply InputCONNECTION DIAGRAMS8-Lead Plastic SOIC (R) Package8-Lead Ceramic DIP (Q) PackageGPOS1GNEG28VPOS7VOUTAD603TOP VIEWVINP3(Not to Scale)6VNEG5COMM4FDBKORDERING GUIDEPart NumberAD603ARAD603AQAD603SQ/883B*AD603-EBAD603ACHIPSAD603AR-REELAD603AR-REEL7Temperature Range–40°C to +85°C–40°C to +85°C–55°C to +125°C–40°C to +85°C–40°C to +85°C–40°C to +85°CPackageDescription8-Lead SOIC8-Lead Ceramic DIP8-Lead Ceramic DIPEvaluation BoardDie13\" Reel7\" ReelPackageOptionSO-8Q-8Q-8SO-8SO-8*Refer to AD603 Military data sheet. Also available as 5962-9457203MPA.CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readilyaccumulate on the human body and test equipment and can discharge without detection. Althoughthe AD603 features proprietary ESD protection circuitry, permanent damage may occur on devicessubjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recom-mended to avoid performance degradation or loss of functionality.WARNING!ESD SENSITIVE DEVICEREV. C–3–
AD603
THEORY OF OPERATIONThe AD603 comprises a fixed-gain amplifier, preceded by abroadband passive attenuator of 0dB to 42.14 dB, having again-control scaling factor of 40 dB per volt. The fixed gain islaser-trimmed in two ranges, to either 31.07 dB (×35.8) or50dB (×358), or may be set to any range in between using oneexternal resistor between Pins 5 and 7. Somewhat higher gaincan be obtained by connecting the resistor from Pin 5 to com-mon, but the increase in output offset voltage limits themaximum gain to about 60 dB. For any given range, the band-width is independent of the voltage-controlled gain. This systemprovides an under- and overrange of 1.07 dB in all cases;for example, the overall gain is –11.07 dB to 31.07 dB in themaximum-bandwidth mode (Pin 5 and Pin 7 strapped).This X-AMP structure has many advantages over former methodsof gain-control based on nonlinear elements. Most importantly,the fixed-gain amplifier can use negative feedback to increase itsaccuracy. Since large inputs are first attenuated, the amplifierinput is always small. For example, to deliver a ±1 V output inthe –1 dB/+41 dB mode (that is, using a fixed amplifier gain of41.07 dB) its input is only 8.84 mV; thus the distortion can bevery low. Equally important, the small-signal gain and phaseresponse, and thus the pulse response, are essentially indepen-dent of gain.Figure 1 is a simplified schematic. The input attenuator is aseven-section R-2R ladder network, using untrimmed resistorsof nominally R = 62.5 Ω, which results in a characteristic resis-tance of 125 Ω ± 20%. A shunt resistor is included at the inputand laser trimmed to establish a more exact input resistance of100 Ω ± 3%, which ensures accurate operation (gain and HPcorner frequency) when used in conjunction with external resistorsor capacitors.The nominal maximum signal at input VINP is 1 V rms (±1.4 Vpeak) when using the recommended ±5 V supplies, althoughoperation to ±2 V peak is permissible with some increase in HFdistortion and feedthrough. Pin 4 (SIGNAL COMMON) mustbe connected directly to the input ground; significant impedance inthis connection will reduce the gain accuracy.The signal applied at the input of the ladder network is attenu-ated by 6.02 dB by each section; thus, the attenuation to each ofthe taps is progressively 0 dB, 6.02 dB, 12.04 dB, 18.06 dB,24.08 dB, 30.1 dB, 36.12 dB and 42.14 dB. A unique circuittechnique is employed to interpolate between these tap-points,indicated by the “slider” in Figure 1, thus providing continuousattenuation from 0 dB to 42.14 dB. It will help, in understandingthe AD603, to think in terms of a mechanical means for movingthis slider from left to right; in fact, its “position” is controlledby the voltage between Pins 1 and 2. The details of the gain-control interface are discussed later.The gain is at all times very exactly determined, and a linear-in-dB relationship is automatically guaranteed by the exponentialnature of the attenuation in the ladder network (the X-AMPprinciple). In practice, the gain deviates slightly from the ideallaw, by about ±0.2 dB peak (see, for example, Figure 16).Noise PerformanceAn important advantage of the X-AMP is its superior noise per-formance. The nominal resistance seen at inner tap points is41.7 Ω (one third of 125 Ω), which exhibits a Johnson noise-spectral density (NSD) of 0.83 nV/√Hz (that is, √4kTR) at 27°C,which is a large fraction of the total input noise. The first stageof the amplifier contributes a further 1nV/√Hz, for a total inputnoise of 1.3 nV/√Hz. It will be apparent that it is essential to usea low resistance in the ladder network to achieve the very lowspecified noise level. The signal’s source impedance forms avoltage divider with the AD603’s 100 Ω input resistance. Insome applications, the resulting attenuation may be unaccept-able, requiring the use of an external buffer or preamplifier tomatch a high impedance source to the low impedance AD603.The noise at maximum gain (that is, at the 0 dB tap) dependson whether the input is short-circuited or open-circuited: whenshorted, the minimum NSD of slightly over 1 nV/√Hz is achieved;when open, the resistance of 100 Ω looking into the first tapgenerates 1.29 nV/√Hz, so the noise increases to a total of1.63 nV/√Hz. (This last calculation would be important if theAD603 were preceded by, for example, a 900 Ω resistor to allowoperation from inputs up to 10 V rms.) As the selected tapmoves away from the input, the dependence of the noise onsource impedance quickly diminishes.Apart from the small variations just discussed, the signal-to-noise (S/N) ratio at the output is essentially independent of theattenuator setting. For example, on the –11 dB/+31 dB rangethe fixed gain of ×35.8 raises the output NSD to 46.5 nV/√Hz.Thus, for the maximum undistorted output of 1V rms and a1MHz bandwidth, the output S/N ratio would be 86.6 dB, thatis, 20 log (1 V/46.5 µV).VPOSVNEGGPOSSCALINGREFERENCEPRECISION PASSIVEINPUT ATTENUATORFIXED GAINAMPLIFIERVOUTVGGNEGGAINCONTROLINTERFACEAD6036.44k⍀*FDBK694⍀*0dBVINP–6.02dB–12.04dB–18.06dB–24.08dB–30.1dB–36.12dB–42.14dBR2RR2RR2RR2RR2RR2RRR*NORMAL VALUES20⍀*COMMR = 2R LADDER NETWORKFigure 1.Simplified Block Diagram of the AD603–4–REV. C
AD603
The Gain-Control InterfaceThe attenuation is controlled through a differential, high-impedance (50 MΩ) input, with a scaling factor which islaser-trimmed to 40 dB per volt, that is, 25 mV/dB. An internalbandgap reference ensures stability of the scaling with respect tosupply and temperature variations.When the differential input voltage VG = 0 V, the attenuator“slider” is centered, providing an attenuation of 21.07 dB. Forthe maximum bandwidth range, this results in an overall gain of10 dB (= –21.07 dB + 31.07 dB). When the control input is–500mV, the gain is lowered by 20 dB (= 0.500 V × 40dB/V),to –10 dB; when set to +500 mV, the gain is increased by 20dB, to30 dB. When this interface is overdriven in either direction, thegain approaches either –11.07 dB (= –42.14 dB + 31.07 dB) or31.07 dB (= 0 + 31.07 dB), respectively. The only constraint onthe gain-control voltage is that it be kept within the common-moderange (–1.2 V to +2.0 V assuming +5 V supplies) of the gaincontrol interface.The basic gain of the AD603 can thus be calculated using thefollowing simple expression:Gain (dB) = 40 VG + 10(1)where VG is in volts. When Pins 5 and 7 are strapped (see nextsection) the gain becomesGain (dB) = 40 VG + 20 for 0 to +40 dBandGain (dB) = 40 VG + 30 for +10 to +50 dB(2)The high impedance gain-control input ensures minimal loadingwhen driving many amplifiers in multiple channel or cascadedapplications. The differential capability provides flexibility inchoosing the appropriate signal levels and polarities for variouscontrol schemes.For example, if the gain is to be controlled by a DAC providinga positive only ground-referenced output, the “Gain ControlLO” (GNEG) pin should be biased to a fixed offset of +500mV,to set the gain to –10 dB when “Gain Control HI” (GPOS) is atzero, and to 30 dB when at +1.00 V.It is a simple matter to include a voltage divider to achieve otherscaling factors. When using an 8-bit DAC having an FS outputof +2.55 V (10 mV/bit), a divider ratio of 2 (generating 5 mV/bit)would result in a gain-setting resolution of 0.2 dB/bit. The useof such offsets is valuable when two AD603s are cascaded, whenvarious options exist for optimizing the S/N profile, as will beshown later.Programming the Fixed-Gain Amplifier Using Pin StrappingDECIBELSVC1VC2GPOSGNEGVINPVPOSVOUTVNEGVPOSVOUTVNEGAD603VINCOMMFDBKa.–10 dB to +30 dB; 90 MHz BandwidthVC1VC2GPOSGNEGVINPVPOSVOUTVNEGVNEG2.15k⍀COMMFDBK5.6pFVPOSVOUTAD603VINb.0 dB to +40 dB; 30 MHz BandwidthVC1VC2GPOSGNEGVINPVPOSVOUTVNEGVNEGVPOSVOUTAD603VINCOMMFDBK18pFc.+10 dB to +50 dB; 9 MHz BandwidthFigure 2.Pin Strapping to Set Gain525048464442403836343230101001kREXT10k100k1M–2:VdB (OUT)VdB (OUT)–1:VdB (OUT)Access to the feedback network is provided at Pin 5 (FDBK).The user may program the gain of the AD603’s output amplifierusing this pin, as shown in Figure 2. There are three modes: inthe default mode, FDBK is unconnected, providing the range+9 dB/+51 dB; when VOUT and FDBK are shorted, the gain islowered to –11 dB/+31 dB; when an external resistor is placedbetween VOUT and FDBK any intermediate gain can be achieved,for example, –1 dB/+41 dB. Figure 3 shows the nominal maxi-mum gain versus external resistor for this mode.Figure 3.Gain vs. REXT, Showing Worst-Case LimitsAssuming Internal Resistors Have a Maximum Toleranceof 20%REV. C–5–
AD603
Optionally, when a resistor is placed from FDBK to COMM,higher gains can be achieved. This fourth mode is of limitedvalue because of the low bandwidth and the elevated output off-sets; it is thus not included in Figure 2.The gain of this amplifier in the first two modes is set by theratio of on-chip laser-trimmed resistors. While the ratio of theseresistors is very accurate, the absolute value of these resistorscan vary by as much as ±20%. Thus, when an external resistoris connected in parallel with the nominal 6.44 kΩ ± 20% inter-nal resistor, the overall gain accuracy is somewhat poorer. Theworst-case error occurs at about 2 kΩ (see Figure 4).1.21.00.80.6DECIBELS0.40.20.0–0.2–0.4–0.6–0.8–1.0
8010
100
1k
REXT
10k
100k
1M
9085VdB (OUT) – VdB (OREF)–1:VdB (OUT) – (–1):VdB (OREF)There are several ways of connecting the gain-control inputs incascaded operation. The choice depends on whether it is impor-tant to achieve the highest possible Instantaneous Signal-to-NoiseRatio (ISNR), or, alternatively, to minimize the ripple in the gainerror. The following examples feature the AD603 programmedfor maximum bandwidth; the explanations apply to other gain/bandwidth combinations with appropriate changes to the arrange-ments for setting the maximum gain.Sequential Mode (Optimal S/N Ratio)In the sequential mode of operation, the ISNR is maintained atits highest level for as much of the gain control range possible.Figure 5 shows the SNR over a gain range of –22 dB to +62 dB,assuming an output of 1 V rms and a 1 MHz bandwidth; Figure6 shows the general connections to accomplish this. Here, boththe positive gain-control inputs (GPOS) are driven in parallel bya positive-only, ground-referenced source with a range of 0 V to+2 V, while the negative gain-control inputs (GNEG) arc biasedby stable voltages to provide the needed gain-offsets. These volt-ages may be provided by resistive dividers operating from acommon voltage reference.S/N RATIO – dB757065605550–0.2Figure 4.Worst-Case Gain Error, Assuming Internal Resis-tors Have a Maximum Tolerance of –20% (Top Curve) or+20% (Bottom Curve)While the gain-bandwidth product of the fixed-gain amplifier isabout 4 GHz, the actual bandwidth is not exactly related to themaximum gain. This is because there is a slight enhancing of theac response magnitude on the maximum bandwidth range, dueto higher order poles in the open-loop gain function; this mildpeaking is not present on the higher gain ranges. Figure 2 showshow optional capacitors may be added to extend the frequencyresponse in high gain modes.CASCADING TWO AD603S0.20.61.0VC1.41.82.2Figure 5.SNR vs. Control Voltage—Sequential Control(1 MHz Bandwidth)Two or more AD603s can be connected in series to achievehigher gain. Invariably, ac coupling must be used to prevent thedc offset voltage at the output of each amplifier from overload-ing the following amplifier at maximum gain. The required highpass coupling network will usually be just a capacitor, chosen toset the desired corner frequency in conjunction with the well-defined 100 Ω input resistance of the following amplifier.For two AD603s, the total gain-control range becomes 84 dB(two times 42.14 dB); the overall –3 dB bandwidth of cascadedstages will be somewhat reduced. Depending on the pin-strapping,the gain and bandwidth for two cascaded amplifiers can rangefrom –22 dB to +62 dB (with a bandwidth of about 70 MHz) to+22 dB to +102 dB (with a bandwidth of about 6 MHz).The gains are offset (Figure 7) such that A2’s gain is increasedonly after A1’s gain has reached its maximum value. Note thatfor a differential input of –600 mV or less, the gain of a singleamplifier (A1 or A2) will be at its minimum value of –11.07 dB;for a differential input of +600 mV or more, the gain will be atits maximum value of 31.07 dB. Control inputs beyond theselimits will not affect the gain and can be tolerated without dam-age or foldover in the response. This is an important aspect ofthe AD603’s gain-control response. (See the Specifications sec-tion of this data sheet for more details on the allowable voltagerange) The gain is nowGain (dB) = 40VG + GO(3)where VG is the applied control voltage and GO is determinedby the gain range chosen. In the explanatory notes that follow,we assume the maximum-bandwidth connections are used, forwhich GO is –20 dB.–6–REV. C
AD603
A1–40.00dB–42.14dBGPOSVG1VC = 0VGNEG31.07dB–8.93dBA2–51.07dB–42.14dBGPOSVG2GNEG31.07dBOUTPUT–20dBINPUT0dBVO1 = 0.473VVO2 = 1.526Va.0dB0dBGPOSVG1VC = 1.0VGNEG31.07dB31.07dB–11.07dB–42.14dBGPOSVG2GNEG31.07dBOUTPUT20dBINPUT0dBVO1 = 0.473VVO2 = 1.526Vb.0dB0dBGPOSVG1VC = 2.0VGNEG31.07dB–2.14dBGPOSVG2GNEG31.07dBOUTPUT60dB–28.93dB31.07dBINPUT0dBVO1 = 0.473VVO2 = 1.526Vc.Figure 6.AD603 Gain Control Input Calculations for Sequential Control Operation+31.07dB+31.07dB+10dB+28.96dBA1**–11.07dBA2–8.93dB0.473GAIN(dB)–22.140–200.50–11.07dB1.5261.0201.50402.060VC (V)62.14When VG = +2.0 V, the gain of A1 is pinned at 31.07 dB andthat of A2 is near its maximum value of 28.93 dB, resulting inan overall gain of 60 dB (see Figure 6c). This mode of operationis further clarified by Figure 8, which is a plot of the separategains of A1 and A2 and the overall gain versus the control voltage.Figure 9 is a plot of the gain error of the cascaded amplifiers versusthe control voltage. Figure 10 is a plot of the gain error of thecascaded stages versus the control voltages.7060COMBINED5040A13020100–10–20–30–0.20.20.60.1VC1.41.82.2A2*GAIN OFFSET OF 1.07dB, OR 26.75mVFigure 7.Explanation of Offset Calibration for SequentialControlWith reference to Figure 6, note that VG1 refers to the differen-tial gain-control input to A1 and VG2 refers to the differentialgain-control input to A2. When VG is zero, VG1 = –473 mV andthus the gain of A1 is –8.93 dB (recall that the gain of each indi-vidual amplifier in the maximum-bandwidth mode is –10 dBfor VG = –500 mV and 10 dB for VG = 0 V); meanwhile, VG2 =–1.908 V so the gain of A2 is “pinned” at –11.07 dB. The over-all gain is thus –20 dB. This situation is shown in Figure 6a.When VG = +1.00 V, VG1 = 1.00 V – 0.473 V = +0.526 V,which sets the gain of A1 to at nearly its maximum value of31.07 dB, while VG2 = 1.00 V – 1.526 V = 0.526 V, which setsA2’s gain at nearly its minimum value –11.07 dB. Close analysisshows that the degree to which neither AD603 is completelypushed to its maximum or minimum gain exactly cancels in theoverall gain, which is now +20 dB. This is depicted in Figure 6b.Figure 8. Plot of Separate and Overall Gains in SequentialControlREV. C–7–
OVERALL GAIN – dBAD603
908070GAIN ERROR – dB2.01.51.00.50.0–0.5–1.0–1.5–2.0–0.20.00.2S/N RATIO – dB605040302010–0.2 0.20.61.0VC1.41.82.20.40.60.81.0VC1.21.41.61.82.02.2Figure 9. SNR for Cascaded Stages—Sequential ControlFigure 11. Gain Error for Cascaded Stages–ParallelControl9085802.01.51.0GAIN ERROR – dB0.50.0–0.5–1.0–1.5–2.0–0.20.00.2IS/N RATIO – dB757065605550–0.20.40.60.81.0VC1.21.41.61.82.02.200.20.4VC0.60.81.01.2Figure 10. Gain Error for Cascaded Stages—SequentialControlFigure 12.ISNR for Cascaded Stages–Parallel ControlParallel Mode (Simplest Gain-Control Interface)In this mode, the gain-control of voltage is applied to both inputsin parallel—the GPOS pins of both A1 and A2 are connected tothe control voltage and the GNEW inputs are grounded. Thegain scaling is then doubled to 80dB/V, requiring only a 1.00 Vchange for an 80 dB change of gain:Gain (dB) = 80 VG + GO(4)where, as before GO depends on the range selected; for example,in the maximum-bandwidth mode, GO is +20 dB. Alternatively,the GNEG pins may be connected to an offset voltage of+0.500 V, in which case, GO is –20 dB.The amplitude of the gain ripple in this case is also doubled, asshown in Figure 11, while the instantaneous signal-to-noise ratioat the output of A2 now decreases linearly as the gain increased(Figure 12).Low Gain Ripple Mode (Minimum Gain Error)As can be seen from Figures 9 and 10, the error in the gain isperiodic, that is, it shows a small ripple. (Note that there is alsoa variation in the output offset voltage, which is due to the gaininterpolation, but this is not exact in amplitude.) By offsettingthe gains of A1 and A2 by half the period of the ripple, that is,by 3 dB, the residual gain errors of the two amplifiers can bemade to cancel. Figure 13 shows that much lower gain ripplewhen configured in this manner. Figure 14 plots the ISNR as afunction of gain; it is very similar to that in the “Parallel Mode.”–8–REV. C
AD603
3.02.52.01.5GAIN ERROR – dBTHEORY OF THE AD603A Low Noise AGC Amplifier1.00.50.0–0.5–1.0–1.5–2.0–2.5–3.0–0.10.00.10.20.30.40.5VC0.60.70.80.91.01.1Figure 15 shows the ease with which the AD603 can be connectedas an AGC amplifier. The circuit illustrates many of the pointspreviously discussed: It uses few parts, has linear-in-dB gain,operates from a single supply, uses two cascaded amplifiers insequential gain mode for maximum S/N ratio, and an externalresistor programs each amplifier’s gain. It also uses a simpletemperature-compensated detector.The circuit operates from a single 10 V supply. Resistors R1,R2, R3, and R4 bias the common pins of A1 and A2 at 5 V.This pin is a low impedance point and must have a low impedancepath to ground, here provided by the 100 µF tantalum capacitorsand the 0.1µF ceramic capacitors.The cascaded amplifiers operate in sequential gain. Here, theoffset voltage between the pins 2 (GNEG) of A1 and A2 is1.05V (42.14 dB × 25 mV/dB), provided by a voltage dividerconsisting of resistors R5, R6, and R7. Using standard values,the offset is not exact, but it is not critical for this application.The gain of both A1 and A2 is programmed by resistors R13and R14, respectively, to be about 42 dB; thus the maximumgain of the circuit is twice that, or 84 dB. The gain-controlrange can be shifted up by as much as 20 dB by appropriatechoices of R13 and R14.The circuit operates as follows. A1 and A2 are cascaded.Capacitor C1 and the 100 Ω of resistance at the input of A1form a time-constant of 10 µs. C2 blocks the small dc offsetvoltage at the output of A1 (which might otherwise saturate A2at its maximum gain) and introduces a high-pass corner at about16 kHz, eliminating low frequency noise.00.20.4VC0.60.81.01.2Figure 13.Gain Error for Cascaded Stages–Low RippleMode908580IS/N RATIO – dB757065605550–0.2Figure 14.ISNR vs. Control Voltage–Low Ripple ModeA half-wave detector is used, based on Q1 and R8. The currentinto capacitor CAV is just the difference between the collectorcurrent of Q2 (biased to be 300µA at 300 K, 27°C) and the col-lector current of Q1, which increases with the amplitude of the10VC110.1FTHIS CAPACITOR SETSAGC TIME CONSTANTVAGCC70.1FC10.1FJ1RT100⍀110VR12.49k⍀+C3100F2C40.1FR22.49k⍀10VR132.49k⍀C80.1FC20.1F10VR32.49k⍀+C5100F2C60.1FR42.49k⍀10VR142.49k⍀CAV0.1FR91.54k⍀Q22N3906R101.24k⍀R113.83k⍀Q12N3904R8806⍀5VR124.99k⍀C90.1FA1AD603A2AD603J2C100.1FAGC LINER55.49k⍀5.5VNOTES
1R PROVIDES A 50⍀ INPUT IMPEDANCET
2C3 AND C5 ARE TANTALUM
1V OFFSET FORSEQUENTIAL GAINR61.05k⍀6.5VR73.48k⍀10VFigure 15.A Low Noise AGC AmplifierREV. C–9–
AD603
output signal. The automatic gain control voltage, VAGC, is thetime-integral of this error current. In order for VAGC (and thusthe gain) to remain insensitive to short-term amplitude fluctuationsin the output signal, the rectified current in Q1 must, on average,exactly balance the current in Q2. If the output of A2 is too smallto do this, VAGC will increase, causing the gain to increase, untilQ1 conducts sufficiently.Consider the case where R8 is zero and the output voltage VOUTis a square wave at, say, 455 kHz, which is well above the cornerfrequency of the control loop.During the time VOUT is negative with respect to the base voltageof Q1, Q1 conducts; when VOUT is positive, it is cut off. Sincethe average collector current of Q1 is forced to be 300µA, andthe square wave has a duty-cycle of 1:1, Q1’s collector currentwhen conducting must be 600µA. With R8 omitted, the peakamplitude of VOUT is forced to be just the VBE of Q1 at 600µA,typically about 700 mV, or 2 VBE peak-to-peak. This voltage,hence the amplitude at which the output stabilizes, has a strongnegative temperature coefficient (TC), typically –1.7mV/°C.Although this may not be troublesome in some applications, thecorrect value of R8 will render the output stable with temperature.To understand this, first note that the current in Q2 is madeto be proportional to absolute temperature (PTAT). For themoment, continue to assume that the signal is a square wave.When Q1 is conducting, VOUT is now the sum of VBE and avoltage that is PTAT and which can be chosen to have an equalbut opposite TC to that of the VBE. This is actually nothing morethan an application of the “bandgap voltage reference” principle.When R8 is chosen such that the sum of the voltage across itand the VBE of Q1 is close to the bandgap voltage of about 1.2 V,VOUT will be stable over a wide range of temperatures, provided,of course, that Q1 and Q2 share the same thermal environment.Since the average emitter current is 600 µA during each half-cycle of the square wave a resistor of 833 Ω would add a PTATvoltage of 500 mV at 300 K, increasing by 1.66 mV/°C. In prac-tice, the optimum value will depend on the type of transistorused and, to a lesser extent, on the waveform for which thetemperature stability is to be optimized; for the inexpensive2N3904/2N306 pair and sine wave signals, the recommendedvalue is 806Ω.This resistor also serves to lower the peak current in Q1 whenmore typical signals (usually, sinusoidal) are involved, and the1.8 kHz LP filter it forms with CAV helps to minimize distortiondue to ripple in VAGC. Note that the output amplitude undersine wave conditions will be higher than for a square wave, sincethe average value of the current for an ideal rectifier would be0.637 times as large, causing the output amplitude to be1.88 (=1.2/0.637) V, or 1.33 V rms. In practice, the somewhatnonideal rectifier results in the sine wave output being regulatedto about 1.4 V rms, or 3.6 V p-p.The bandwidth of the circuit exceeds 40 MHz. At 10.7 MHz,the AGC threshold is 100 µV (–67 dBm) and its maximum gainis 83 dB (20 log 1.4V/100 µV). The circuit holds its output at1.4 V rms for inputs as low as –67 dBm to +15 dBm (82 dB),where the input signal exceeds the AD603’s maximum inputrating. For a 30 dBm input at 10.7 MHz, the second harmonicis 34 dB down from the fundamental and the third harmonic is35 dB down.CAUTIONCareful component selection, circuit layout, power-supplydecoupling, and shielding are needed to minimize the AD603’ssusceptibility to interference from radio and TV stations, etc. Inbench evaluation, we recommend placing all of the componentsin a shielded box and using feedthrough decoupling networksfor the supply voltage. Circuit layout and construction are alsocritical, since stray capacitances and lead inductances can formresonant circuits and are a potential source of circuit peaking,oscillation, or both.–10–REV. C
2.502.0045MHz1.50Bd – 1.0070MHzRO10.7MHzRR0.50E NIA0.00G–0.50455kHz–1.0070MHz–1.50–0.5–0.4–0.3–0.2–0.10.00.20.30.40.50.6GAIN VOLTAGE – VoltsFigure 16.Gain Error vs. Gain ControlVoltage at 455 kHz, 10.7 MHz, 45 MHz,70 MHzBd – NIAG100k
1M10M100M
FREQUENCY – Hz
Figure 19.Frequency and Phase Response vs. Gain (Gain = +30dB, PIN = –30 dBm, Pin 5 Connected to Pin 7)10dB/DIVFigure 22.Third Order Intermodula-tion Distortion at 455kHz (10× ProbeUsed to HP3585A Spectrum Analyzer,Gain = 0dB, PIN = 0dBm, Pin 5 Con-nected to Pin 7)REV. CBd – NIAG100k1M10M100MFREQUENCY – Hz Figure 17.Frequency and Phase Response vs. Gain (Gain = –10dB, PIN = –30dBm, Pin 5 Connected to Pin 7)7.607.40sn –7.20 YALED7.00 PUORG6.806.606.40–0.6–0.4–0.200.20.40.6GAIN CONTROL VOLTAGE – Volts Figure 20.Group Delay vs. Gain Control Voltage10dB/DIVFigure 23.Third Order Intermodula-tion Distortion at 10.7MHz (10× ProbeUsed to HP3585A Spectrum Analyzer,Gain = 0dB, PIN = 0dBm, Pin 5 Con-nected to Pin 7)–11–
AD603
Bd – NIAG100k1M10M100MFREQUENCY – HzFrequency and PhasedB,IN = –30dBm, Pin 5 Connected to+5V0.1FHP3326ADUALCHANNELSYNTHESIZER100⍀AD60310؋HP3585APROBESPECTRUMANALYZER0.1F511⍀–5VDATELDVC 8500Figure 21.Third Order Intermodula-tion Distortion Test Setups–1.0tloV–1.2 – T–1.4IMIL–1.6 EG–1.8ATL–2.0OV–2.2 TU–2.4PTU–2.6O E–2.8VIT–3.0AGE–3.2N–3.405010020050010002000LOAD RESISTANCE – ⍀Figure 24.Typical Output VoltageSwing vs. Load Resistance (NegativeOutput Swing Limits First) Figure 18. Response vs. Gain (Gain = +10 P Pin 7)AD603
102⍀ –CE100NAD98MPEI TUNP96I94100k1M10M100MFREQUENCY – Hz Figure 25.Input Impedance vs.Frequency (Gain = –10dB)1V1V200nsFigure 28.Gain-Control ChannelResponse Time3.5VINPUT500mV/DIVGND500mV
OUTPUT500mV/DIVGND–1.5V
–44ns50ns456ns Figure 31.Transient Response, G = 0dB, Pin 5 Connected to Pin 7 (Input is 500ns Period, 50% Duty- Cycle Square Wave, Output IsCaptured Using Tektronix 11402 Digitizing Oscilloscope)102⍀ –100CENAD98MPEI TUNP96I94100k1M10M100MFREQUENCY – Hz Figure 26.Input Impedance vs.Frequency (Gain = +10dB)4.5VINPUT GND1V/DIV500mVOUTPUT GND500mV/DIV–500mV–49ns50ns451ns Figure 29.Input Stage Overload Recovery Time, Pin 5 Connected to Pin 7 (Input Is 500ns Period, 50% Duty-Cycle Square Wave, Output Is Captured Using Tektronix 11402 Digitizing Oscilloscope)3.5VINPUT GND100mV/DIV500mV OUTPUT GND500mV/DIV–1.5V–44ns50ns456ns Figure 32.Transient Response, G = +20dB, Pin 5 Connected to Pin 7 (Input is 500 ns Period, 50% Duty- Cycle Square Wave, Output IsCaptured Using Tektronix 11402 Digitizing Oscilloscope)–12–102⍀ –100CENAD98MPEI TUNP96I94100k1M10M100MFREQUENCY – Hz Figure 27.Input Impedance vs. Frequency (Gain = +30dB)8VINPUT GND100mV/DIV1VOUTPUT GND 1V/DIV–2V–49ns50ns451ns Figure 30.Output Stage Overload Recovery Time, Pin 5 Connected to Pin 7 (Input Is 500 ns Period, 50% Duty-Cycle Square Wave, Output Is Captured Using Tektronix 11402 Digitizing Oscilloscope)0–10–20Bd–30 –RR–40PS–50–60100k1M10M100MFREQUENCY – HzFigure 33.PSRR vs. Frequency (WorstCase Is Negative Supply PSRR,Shown Here)REV. C
+5V0.1FHP3326ADUALCHANNELSYNTHESIZERHP3585A100⍀AD60350⍀SPECTRUMANALYZER0.1F–5VDATELDVC 8500Figure 34.Test Setup Used for: NoiseFigure, 3rd Order Intercept and 1 dBCompression Point Measurements0TA = 25؇CTEST SETUP–5FIGURE 34mBd – –10LEVEL TU–15PNI–20–2510305070INPUT FREQUENCY – MHzFigure 37.1 dB Compression Point,–10 dB/+30 dB Mode, Gain = 30 dBREV. C232130MHzTA = 25؇CRS = 50⍀1970MHzTEST SETUPFIGURE 34Bd –17 ERU1550MHzGIF 13ESIO11N10MHz9752021222324252627282930GAIN – dBFigure 35.Noise Figure in –10 dB/+30 dB Mode20TA = 25؇C18TEST SETUPFIGURE 34m30MHzBd 16– LE40MHzVEL14 TUPTU12O70MHz108–20–100INPUT LEVEL – dBmFigure 38.3rd Order Intercept –10 dB/+30 dB Mode, Gain = 10 dB–13–
AD603
211910MHzTA = 25؇CRS = 50⍀TEST SETUPB17FIGURE 34d –20MHz E15RUG13IF ESI11ON9753031323334353637383940GAIN – dBFigure 36.Noise Figure in 0 dB/+40 dBMode20TA = 25؇C18RS = 50⍀RIN = 50⍀m30MHzRBL = 100⍀dTEST SETUP 16– FIGURE 34LE40MHzVEL14 TUPTU12O70MHz108–40–30–20INPUT LEVEL – dBmFigure 39.3rd Order Intercept, –10 dB/+30 dB Mode, Gain = 30 dBAD603
OUTLINE DIMENSIONSDimensions shown in inches and (mm).8-Lead Cerdip (Q-8)0.005 (0.13)0.055 (1.4)MINMAX850.310 (7.87)0.220 (5.59)14PIN 10.320 (8.13) 0.405 (10.29) MAX0.060 (1.52)0.290 (7.37)0.200 (5.08)0.015 (0.38)MAX0.1500.200 (5.08)(3.81)0.125 (3.18)MIN0.023 (0.58)0.015 (0.38)0.1000.070 (1.78)SEATINGPLANE15°0.014 (0.36)(2.54)0.008 (0.20)BSC0.030 (0.76)0°8-Lead SOIC (SO-8)0.1968 (5.00)0.1890 (4.80)0.1574 (4.00)850.2440 (6.20)0.1497 (3.80)140.2284 (5.80)PIN 10.0500 (1.27)0.0196 (0.50)BSC0.0099 (0.25)؋ 45؇0.0098 (0.25)0.0688 (1.75)0.0040 (0.10)0.0532 (1.35)8؇SEATING0.0192 (0.49)0.0098 (0.25)0؇0.0500 (1.27)PLANE0.0138 (0.35)0.0075 (0.19)0.0160 (0.41)–14–)C .ver( 00/1–0–a1581C.A.S.U NI DETNIRPREV. C
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