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FPGA可编程逻辑器件芯片XCZU9EG- 2FFVB1156I中文规格书

2020-10-21 来源:客趣旅游网
Appendix D: Using the Xilinx Virtual Cable to Debug

XVC Version Register (PCIe-XVC-VSEC only)

This register is populated by the Xilinx tools and is used by the Vivado Design Suite to identifythe specific features of the Debug Bridge IP that is implemented in the hardware design.

XVC Shift Length Register

This register is used to set the scan chain shift length within the debug scan chain.

XVC TMS Register

This register is used to set the TMS data within the debug scan chain.

XVC TDO/TDI Data Register(s)

This register is used for TDO/TDI data access. When using PCIePCI-XVC-VSEC, these tworegisters are combined into a single field. When using AXI-XVC, these are implemented as twoseparate registers.

XVC Control Register

This register is used for XVC control data.

XVC Status Register

This register is used for XVC status information.

XVC Driver and Software

Example XVC driver and software has been provided with the Vivado Design Suite installation,which is available at the following location: /data/xicom/driver/pcie/xvc_pcie.zip. This should be used for reference when integrating the XVCcapability into Xilinx FPGA platform design drivers and software. The provided Linux kernel modedriver and software implement XVC-over-PCIe debug for both PCIe-XVC-VSEC and AXI-XVCdebug bridge implementations.

When operating in PCIe-XVC-VSEC mode, the driver will initiate PCIe configuration transactionsto interface with the FPGA debug network. When operating in AXI-XVC mode, the driver willinitiate 32-bit PCIe Memory BAR transactions to interface with the FPGA debug network. Bydefault, the driver will attempt to discover the PCIe-XVC-VSEC and use AXI-XVC if the PCIe-XVC-VSEC is not found in the PCIe configuration extended capability linked list.

PG195 (v4.1) April 29, 2021

DMA/Bridge Subsystem for PCIe v4.1

Appendix D: Using the Xilinx Virtual Cable to Debug

1.Copy the ZIP file from the Vivado install directory to the FPGA connected Host PC and

extract (unzip) its contents. This file is located at the following path within the Vivadoinstallation directory.

XVC Driver and SW Path: …/data/xicom/driver/pcie/xvc_pcie.zipThe README.txt files within the driver_* and xvcserver directories identify how tocompile, install, and run the XVC drivers and software, and are summarized in the followingsteps. Follow the following steps after the driver and software files have been copied to theHost PC and you are logged in as a user with root permissions.

2.Modify the variables within the driver_*/xvc_pcie_user_config.h file to match your

hardware design and IP settings. Consider modifying the following variables:

•PCIE_VENDOR_ID: The PCIe Vendor ID defined in the PCIe® IP customization.•PCIE_DEVICE_ID: The PCIe Device ID defined in the PCIe® IP customization.

•Config_space: Allows for the selection between using a PCIe-XVC-VSEC or an AXI-XVCperipheral. The default value of AUTO first attempts to discover the PCIe-XVC-VSEC, thenattempts to connect to an AXI-XVC peripheral if the PCIe-XVC-VSEC is not found. A valueof CONFIG or BAR can be used to explicitly select between PCIe®-XVC-VSEC and AXI-XVC implementations, as desired.•config_vsec_id: The PCIe XVC VSEC ID (default 0x0008) defined in the Debug Bridge IPwhen the Bridge Type is configured for From PCIE to BSCAN. This value is only used fordetection of the PCIe®-XVC-VSEC.•config_vsec_rev: The PCIe XVC VSEC Rev ID (default 0x0) defined in the Debug Bridge IPwhen the Bridge Type is configured for From PCIe to BSCAN. This value is only used fordetection of the PCIe-XVC-VSEC.•bar_index: The PCIe BAR index that should be used to access the Debug Bridge IP whenthe Bridge Type is configured for From AXI to BSCAN. This BAR index is specified as acombination of the PCIe IP customization and the addressable AXI peripherals in yoursystem design. This value is only used for detection of an AXI-XVC peripheral.•bar_offset: PCIe BAR Offset that should be used to access the Debug Bridge IP when theBridge Type is configured for From AXI to BSCAN. This BAR offset is specified as acombination of the PCIe IP customization and the addressable AXI peripherals in yoursystem design. This value is only used for detection of an AXI-XVC peripheral.3.Move the source files to the directory of your choice. For example, use:

/home/username/xil_xvc or /usr/local/src/xil_xvc

4.Make sure you have root permissions and change to the directory containing the driver files.

# cd /driver_*/

5.Compile the driver module:

# make install

The kernel module object file will be installed as:

PG195 (v4.1) April 29, 2021

DMA/Bridge Subsystem for PCIe v4.1

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