Logic circuit testable as an inverter pair and ope

专利名称：Logic circuit testable as an inverter pair and

operable as a flip- flop

发明人：Tsuneo Kinoshita申请号：US06/888273申请日：19860722公开号：US04728823A公开日：19880301

摘要：A logic circuit on a substrate is switchable between a test mode and anoperational mode. First and second NOR gates are cross- coupled and may be switchedbetween an operational mode and a test mode by the application of a control signal tofirst and second transfer gates coupled to the inputs of the NOR gates. The first NORgate includes a p- type region and an n-type region formed in said substrate andtraversed with first and second conductive layers insulated from the p and n-typeregions. Thus, the first NOR gate includes two p-channel transistors and two n-channeltransistors. The second NOR gate is also formed by a p-type region and an n-type regiontraversed with third and fourth conductive layers. Thus, the second NOR gate alsoincludes two p-channel transistors and two n-channel transistors. The transfer gates arelocated on the substrate between the first and second NOR gates. Both transfer gatesinclude an n-type region formed in the substrate with a conductive layer disposed overthe n-type region. In the operational mode, the cross- coupled NOR gates may performas a flip-flop. In the test mode, each NOR gate essentially becomes an inverter.

申请人：TOKYO SHIBAURA DENKI KABUSHIKI KAISHA

代理机构：Cushman, Darby & Cushman

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