一﹑系统设计总述（本次为课设，不是实验报告，请按模板修改） 1. 实验目的
（1）了解点阵字符的产生和显示原理。
（2）了解FPGA芯片和16×16点阵管的工作原理。 （3）熟练掌握连线与对硬件的使用。
2．实验原理
16×16LED点阵管的点亮是由其列选信号和其行选信号所共同控制的。其行选 号
共有15个为L0—L15，列选信号有四个为SEL3—SEL0。当其列选信号选中某一列时，在给所需要的行一个高电平，就能控制其点亮。例如当SEL0—SEL3为0000时，给L0一个高电平，就能使第一行第一列对应的点亮。
3. 实验内容
（1）上机调试所编写好的程序。 （2）将程序下载到芯片上。 （3）实验连线及功能测试。
二﹑系统总实验原理图
八进制计数器是用于切换显示花样，CLK1是用于扫描列的信号，其频率应大于人眼的视觉效果。DOTOUT和SELOUT则是用于控制16×16点阵管的点亮。
三﹑系统子程序设计
1.八进制计数器设计
JY是八进制计数器，当每一个时钟上升沿到来时，计数器就记一次数，16×16点阵
管就显示一个字。例如当其为0000时，就显示“进”字。
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其程序如下 library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity jy is
port(clk,rst:in std_logic;
jout:buffer std_logic_vector(3 downto 0)); end jy;
architecture b of jy is begin
process(clk,rst) begin
if rst='1' then jout<=\"0000\";
elsif clk'event and clk='1' then if jout=7 then jout<=\"0000\" ; else jout<=jout+1; end if; end if; end process; end b; 其仿真波形
2. 行列驱动设计
此程序是文字显示，即“进德修业，精益求精”通过计数器的计数而循环显示。 其程序如下 library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity k is
port(clk,rst:in std_logic;
din :in std_logic_vector(3 downto 0); dotout:out std_logic_vector(15 downto 0);
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selout:buffer std_logic_vector(3 downto 0)); end k;
architecture a of k is begin
process(clk,rst,din) begin
if rst='1' then dotout<=\"0000000000000000\"; selout<=\"0000\" ;
elsif clk'event and clk='1' then if selout=15 then selout<=\"0000\" ; else selout<=selout+1; end if; case din is when \"0000\"=>
case selout is
when \"0000\" =>dotout<=\"0000000000001000\"; when \"0001\" =>dotout<=\"0001000000001000\"; when \"0010\" =>dotout<=\"0101001100001000\"; when \"0011\" =>dotout<=\"0011010100011000\"; when \"0100\" =>dotout<=\"0001100011101000\"; when \"0101\" =>dotout<=\"0000001001101000\"; when \"0110\" =>dotout<=\"0000101001001000\"; when \"0111\" =>dotout<=\"0000101010001000\"; when \"1000\" =>dotout<=\"0011111110000100\"; when \"1001\" =>dotout<=\"0000101000000100\"; when \"1010\" =>dotout<=\"0000101000000100\";
when \"1011\" =>dotout<=\"0011111111111100\"; when \"1100\" =>dotout<=\"0000101000000100\"; when \"1101\" =>dotout<=\"0000001000001000\"; when \"1110\" =>dotout<=\"0000000000000000\"; when \"1111\" =>dotout<=\"0000000000000000\"; when others=>dotout<=null; end case; when \"0001\"=>
case selout is
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when \"0000\" =>dotout<=\"0000101000000000\"; when \"0001\" =>dotout<=\"0001010000000000\"; when \"0010\" =>dotout<=\"0010111111111100\"; when \"0011\" =>dotout<=\"0101000000000000\"; when \"0100\" =>dotout<=\"0100000000100000\"; when \"0101\" =>dotout<=\"0100111011000000\"; when \"0110\" =>dotout<=\"0010101010111000\"; when \"0111\" =>dotout<=\"0010101010001000\"; when \"1000\" =>dotout<=\"0010111011001000\"; when \"1001\" =>dotout<=\"0111101010101000\"; when \"1010\" =>dotout<=\"0010111010001000\";
when \"1011\" =>dotout<=\"0010101010001000\"; when \"1100\" =>dotout<=\"0010101011001000\"; when \"1101\" =>dotout<=\"0010111010111000\"; when \"1110\" =>dotout<=\"0000000000010000\"; when \"1111\" =>dotout<=\"0000000000000000\"; when others=>dotout<=null; end case; when \"0010\"=>
case selout is
when \"0000\" =>dotout<=\"0000001000000000\"; when \"0001\" =>dotout<=\"0000010000000000\"; when \"0010\" =>dotout<=\"0000111111111100\"; when \"0011\" =>dotout<=\"0001000000000000\"; when \"0100\" =>dotout<=\"0010011111111000\"; when \"0101\" =>dotout<=\"0100010000000000\"; when \"0110\" =>dotout<=\"0000100010000000\"; when \"0111\" =>dotout<=\"0001000101010100\"; when \"1000\" =>dotout<=\"0011001010101000\"; when \"1001\" =>dotout<=\"0111010101010000\"; when \"1010\" =>dotout<=\"0010101010100000\";
when \"1011\" =>dotout<=\"0010110101000000\"; when \"1100\" =>dotout<=\"0011001010000000\"; when \"1101\" =>dotout<=\"0010000100000000\"; when \"1110\" =>dotout<=\"0000000010000000\";
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when \"1111\" =>dotout<=\"0000000000000000\"; when others=>dotout<=null; end case; when \"0011\"=>
case selout is
when \"0000\" =>dotout<=\"0000110000000100\"; when \"0001\" =>dotout<=\"0000011000000100\"; when \"0010\" =>dotout<=\"0000001100000100\"; when \"0011\" =>dotout<=\"0000000100000100\"; when \"0100\" =>dotout<=\"0111111111111100\"; when \"0101\" =>dotout<=\"0000000000000100\"; when \"0110\" =>dotout<=\"0000000000000100\"; when \"0111\" =>dotout<=\"0000000000000100\"; when \"1000\" =>dotout<=\"0000000000000100\"; when \"1001\" =>dotout<=\"0111111111111100\"; when \"1010\" =>dotout<=\"0000000100000100\";
when \"1011\" =>dotout<=\"0000001100000100\"; when \"1100\" =>dotout<=\"0000011000000100\"; when \"1101\" =>dotout<=\"0000110000000100\"; when \"1110\" =>dotout<=\"0001000000000100\"; when \"1111\" =>dotout<=\"0001000000000100\"; when others=>dotout<=null; end case; when \"0100\"=>
case selout is
when \"0000\" =>dotout<=\"0000101011000000\"; when \"0001\" =>dotout<=\"0000011100000000\"; when \"0010\" =>dotout<=\"0111111111111110\"; when \"0011\" =>dotout<=\"0000011100000000\"; when \"0100\" =>dotout<=\"0000101010000000\"; when \"0101\" =>dotout<=\"0001001001000000\"; when \"0110\" =>dotout<=\"0000000000100000\"; when \"0111\" =>dotout<=\"0010001000000000\"; when \"1000\" =>dotout<=\"0010101011111110\";
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when \"1001\" =>dotout<=\"0010101010101000\"; when \"1010\" =>dotout<=\"1111111010101000\";
when \"1011\" =>dotout<=\"0010101010101100\"; when \"1100\" =>dotout<=\"0010101010101010\"; when \"1101\" =>dotout<=\"0010101011111110\"; when \"1110\" =>dotout<=\"0000001000000000\"; when \"1111\" =>dotout<=\"0000001000100000\"; when others=>dotout<=null; end case; when \"0101\"=>
case selout is
when \"0000\" =>dotout<=\"0000100001000100\"; when \"0001\" =>dotout<=\"0000100010000100\"; when \"0010\" =>dotout<=\"0100100101111100\"; when \"0011\" =>dotout<=\"0010101001000100\"; when \"0100\" =>dotout<=\"0001110001000100\"; when \"0101\" =>dotout<=\"0000100001111100\"; when \"0110\" =>dotout<=\"0000100001000100\"; when \"0111\" =>dotout<=\"0000100001000100\"; when \"1000\" =>dotout<=\"0000100001111100\"; when \"1001\" =>dotout<=\"0001110001000100\"; when \"1010\" =>dotout<=\"0010101001000100\";
when \"1011\" =>dotout<=\"0100100101111100\"; when \"1100\" =>dotout<=\"0000100010000100\"; when \"1101\" =>dotout<=\"0000100001000100\"; when \"1110\" =>dotout<=\"0000000000000000\"; when \"1111\" =>dotout<=\"0000000000000000\"; when others=>dotout<=null; end case; when \"0110\"=>
case selout is
when \"0000\" =>dotout<=\"0010000000010000\"; when \"0001\" =>dotout<=\"0010000000100000\"; when \"0010\" =>dotout<=\"0010000001000000\"; when \"0011\" =>dotout<=\"0010100010000000\";
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when \"0100\" =>dotout<=\"0010010100000100\"; when \"0101\" =>dotout<=\"0010001000000010\"; when \"0110\" =>dotout<=\"1111111111111110\"; when \"0111\" =>dotout<=\"0010001000000000\"; when \"1000\" =>dotout<=\"1010010100000000\"; when \"1001\" =>dotout<=\"0110100010000000\"; when \"1010\" =>dotout<=\"0011000001000000\";
when \"1011\" =>dotout<=\"0010000000100000\"; when \"1100\" =>dotout<=\"0010000000010000\"; when \"1101\" =>dotout<=\"0000000000001000\"; when \"1110\" =>dotout<=\"0000000000000100\"; when \"1111\" =>dotout<=\"0000000000001000\"; when others=>dotout<=null; end case; when \"0111\"=>
case selout is
when \"0000\" =>dotout<=\"0000101011000000\"; when \"0001\" =>dotout<=\"0000011100000000\"; when \"0010\" =>dotout<=\"0111111111111110\"; when \"0011\" =>dotout<=\"0000011100000000\"; when \"0100\" =>dotout<=\"0000101010000000\"; when \"0101\" =>dotout<=\"0001001001000000\"; when \"0110\" =>dotout<=\"0000000000100000\"; when \"0111\" =>dotout<=\"0010001000000000\"; when \"1000\" =>dotout<=\"0010101011111110\"; when \"1001\" =>dotout<=\"0010101010101000\"; when \"1010\" =>dotout<=\"1111111010101000\";
when \"1011\" =>dotout<=\"0010101010101100\"; when \"1100\" =>dotout<=\"0010101010101010\"; when \"1101\" =>dotout<=\"0010101011111110\"; when \"1110\" =>dotout<=\"0000001000000000\"; when \"1111\" =>dotout<=\"0000001000100000\"; when others=>dotout<=null; end case; when others=>null;
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end case; end if; end process; end a;
其仿真波形如下
四﹑总原理图仿真波形
将上述模块连接起来组成原理图，进行编译仿真。
五﹑实验总结
虽然这次EDA课程设计的时间并不算长，但是我却收获颇丰。不仅把以前所学的东西重新复习了一遍，而且还把所学的知识进行了总结，使我清楚的了解了总体的框架，知识更加紧凑。
在编写程序的过程中，通过不断的查阅课本以及自我的思考，是我熟练的掌握了VHDL语言的语法规则，并且能够独立的完成。我也熟练的掌握了对程序的编译仿真等过程。通过和同组的同学的积极配合，最终我们顺利的完成了任务。
在完成任务后，我有很高的成就感。这使我对这门课产生了更大的兴趣，以后希望自己能够做出更多的使用的东西来。
通过这次课程设计使我懂得了理论与实际相结合是很重要的，只有理论知识是远远不够的，只有把所学的理论知识与实践相结合起来，从理论中得出结论，从而提高自己的实际动手能力和独立思考的能力。
总之，很高兴能有机会进行这次课设，使我从中学到了很多，希望以后能有更多的机会锻炼自己的动手能力。
六﹑参考文献
EDA技术与实验 李国洪 胡辉 沈明山 等编著
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