专利名称：ALGORITHM FOR VECTORIZATION AND
MEMORY COALESCING DURING COMPILING
发明人：Vinod Grover,Manjunath Kudlur,Michael
Murphy
申请号：US13660986申请日：20121025
公开号：US20130117548A1公开日：20130509
专利附图：
摘要：One embodiment of the present invention sets forth a technique for reducingthe number of assembly instructions included in a computer program. The technique
involves receiving a directed acyclic graph (DAG) that includes a plurality of nodes, whereeach node includes an assembly instruction of the computer program, hierarchicallyparsing the plurality of nodes to identify at least two assembly instructions that arevectorizable and can be replaced by a single vectorized assembly instruction, andreplacing the at least two assembly instructions with the single vectorized assemblyinstruction.
申请人：NVIDIA Corporation
地址：Santa Clara CA US
国籍：US
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