专利名称:Current selective D flip-flop circuit发明人:Ye Dajun,Chee Piew Yoong,Yong Siong Siew申请号:US10801455申请日:20040316
公开号:US20050206424A1公开日:20050922
专利附图:
摘要:An embodiment of a current selective D flip-flop circuit comprises a D flip-flop,a current selector and a current multiplier is disclosed. The current selector is used forreceiving and summing at least two currents to form a summed current and having acurrent comparator for comparing the summed current with one of the at least two
currents and selecting one of the at least two currents as an output current. The outputcurrent is steered through the current multiplier for biasing the D flip-flop.
申请人:Ye Dajun,Chee Piew Yoong,Yong Siong Siew
地址:Singapore SG,Singapore SG,Singapore SG
国籍:SG,SG,SG
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