CIRCUIT AND METHOD FOR TESTING TRANSISTOR(S)

专利名称：CIRCUIT AND METHOD FOR TESTING

TRANSISTOR(S)

发明人：Guangliang SHANG,Yun Sik IM,Seung Woo

HAN

申请号：US14573100申请日：20141217

公开号：US20160109504A1公开日：20160421

专利附图：

摘要：Disclosed is a circuit and method for testing transistor(s). The circuit is used fortesting a set of transistors including at least two transistors, wherein the circuit

comprises: a first power supply voltage terminal connected to first electrodes of therespective transistors; a first control signal terminal connected to control electrodes ofthe respective transistors; and a set of test terminals including at least two testterminals, wherein the test terminals are connected to second electrodes of thecorresponding transistors, respectively. According to the circuit disclosed in the presentdisclosure, it can be achieved that the bias voltages can be applied to the plurality oftransistors to be tested simultaneously. Further, the current characteristics of thetransistors are tested respectively, which avoids applying the bias voltage to the pluralityof transistor to be tested one by one, thus reducing the time consumed in test andimproving the testing efficiency

申请人：BOE TECHNOLOGY GROUP CO., LTD.

地址：Beijing CN

国籍：CN

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