State machine architecture providing increased res

专利名称：State machine architecture providing

increased resolution of output timing

发明人：Phillip E. Mattison申请号：US07/679379申请日：19910402公开号：US05159278A公开日：19921027

摘要：A circuit allows for improved flexibility in the timing of device output, forexample, from a state machine. Output for the device is placed in a first register. Theoutput is forwarded from the first register to a second register. The first register and thesecond register are clocked on different edges of a clock signal. A selector selectscontents of the first register or contents of the second register as the device output foran external device. The selector may be controlled by the contents of one or more flip-flops. When the device is a state machine, the output of each flip-flop may also be usedas feedback to the state machine.

申请人：VLSI TECHNOLOGY, INC.

代理人：Douglas L. Weller

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